Oscillator with AND and NOT gates?

Hi,
I've been recently working with logic gates and that's when this struck me.If an AND gate and an inverter are hooked up as per the attached schematic, can point A function as an oscillator?Assume that the gate inputs float high.
If so
1)What would be the frequencies of the oscillations if the gates used are a)CMOS b)TTL ?
2)Would the frequency change with the input voltage ?
3)Is this implemented elsewhere?

Thank you for reading my question.

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iceng2 years ago

To find the approximate frequency read the rise and fall timing of the gates in question add the times and you have the wave length and you know how to compute the frequency.

CMOS Fq will change with voltage as the PDF gives transition times for 5v 10v and 15v....

-max-2 years ago

Try it and see! It is in fact a negative feedback loop. You will learn a lot in discovering why it does or does not.

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Remember that although you are using logic circuits which are designed to be digital, you have made a closed loop control system. This means that thing will act like an analog circuit. (all circuits, including digital circuits really analog in nature, they are made with real transistors like anything else, but since it is usually an open loop config, and we feed in digital HIGH / LOW signals, we get HIGH and LOW outputs. Give the gates, like maybe 2-4 volts instead of 0-5V, you will see the output maybe not be quite HIGH or LOW. the operation of the 'simple' logic gates becomes far more complicated in how the input voltages are related to the output.)

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Since there is no delay in the feedback loop, the loop response will be really fast. (in other words, the output controls the input almost instantly.) Since the output responses so quickly to the input, and assuming the parts have a finite gain to them, and that the inputs do not have hysteresis (like Schmitt trigger inputs), and that the transistors take time to turn on and off, (e.i: the slew rate) I think point A will be some random, stable voltage, depending on the internal wiring of the logic gates, like the turn-on voltage for the gates.

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https://www.youtube.com/user/ControlLectures/videos Check out this guy's channel on control therory. There is a whole science behind it, PID stuff, phase angle, the whole shebang!

Its a positive feedback loop, that's why it oscillates.

In my experience, positive feedback in a circuit causes the output to either slam to one or the other rails, (with super strong hysteresis.) like this classic op amp circuit.

http://www.electronics-tutorials.ws/systems/sys29.gif

The output will be extremely unstable and fly off to +/- infinity, if it was not limited by the voltage rails. Good luck making the output not slam against the voltage rails. Regardless once it does, it is stable. Either close to 0V or Vcc output. Having strong negative feedback while there is something slowing down the loop causes parasitic oscillation, like a poorly designed LDO regulator without the right amount of capacitance on the output.

Your experience is very limited as of yet.

When you learn enough about the mathematical basic of feedback control, you will be able to correct your misunderstanding.

+1

iceng seandogue2 years ago

+1 for Steve

When younger then MAX and not as parasitic, I used to watch and enjoy Fantasia in Paris whenever I had a chance in a reel movie theater.

Are you to argue to me that negative feedback loops do not oscillate? I know for a FACT that they CAN. Especially when the conditions explained are true. (I will not claim that positive feedback does not lead to oscillation, especially in far more complicated control loop systems, but for this specific example.)

http://en.wikipedia.org/wiki/Negative_feedback_amplifier

I also know enough intuitively and experimentally about negative feedback loops to know what I said is true to some degree, at least in practice.

Correct me if I am wrong, but what is shown in the schematic is in fact a negative feedback loop. The NOT gate INVERTING device, and the AND gate just passes the signal though without doing much to it, if the other input is high.

You do not understand. Negative feedback loops oscillate when the effects of phase shifts and otherwise cause the poles of the Laplace transfer function representing the network move into the real positive pole-zero diagram plane: Long and short of it: the feedback becomes positive and not negative.

Yes, you are wrong, what is shown in the schematic is a positive feedback loop.

+1

Wait, I was thinking of the fourier transform, the 2 things I think are inverse function of earchther, like derivitives and intergals, correct?

No, Completely different things. The Laplace transform allows the algebraic solution of complex diffential equations, in the frequency domain, the Fourier is an analytical tool for determining the harmonic content of an arbitrary waveform.

Yeah, I was thinking of fourier, the conversion between the "time domain" and "frequency domain" and all that.

I think I have heard of that oscillator, I see both negative and positive feedback in it, something more complex then I usually deal with. I will attempt to figure out how it works when I have time.

When why does a positive feedback loop in the op amp circuit just go off towards +/- infinity until it hits the voltage rails????? It doesn't bounce around above and below some value as the system keeps attempting to correct its own error, it just diverges.

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I see what you are saying: Like if the phase shift from a delay in the loop may cause 180 degree shift at a specific frequency with the same 1/2 period or same half cycle, which is the equivalent of inverting. (I have yet to do calculus 3 and learn about how to convert what is seen on a scope to what is seen on a spectrum analyzer, but I do acknowledge this relationship. I think mathematically, laplace transforms I think break apart out all the frequency content of a signal and show all the frequency sine waves that need to be summed together to create the original wave... sort of like a prism with light. That is what I can understand from that technical mumbo jumbo until I get higher education) BUT that is for only one frequency, and I assume the harmonic series (1, 1/2, 1/3, 1/4, etc. etc. ) Will a Proper positive feedback in the sense that I am referring to, (that is, for all frequencies, same 'gain') cause oscillation? I do not think so.

It only diverges if you let it. Add a non-linear element and you can create a very nice sine wave for example.

Hewlett-Packard, the legendary engineering company's first product was a very high quality audio oscillator - Disney Studios was one of the first customers - it was used to help create Fantasia - it was a Wien bridge oscillator, stabilised by a filament lamp.

-max- -max-2 years ago

I should add a correction: parasitic oscillation from a negative feedback loop when

A: "P" (proportional) gain is too high, (it the loop keeps overcorrecting)

B: when there is something that literally delays the signal, like a delay line, and causes a major enough phase shift, so then the correction the loop tries to do is too late to fix it, swings it again the other way, and parasitic oscillation!

C: Million other things like bad PID settings, (I and D is controlled with capacitor's for electronics, you can change the transfer function with them.) I ain't no expert though, I can't even get my quadcopter tuned all that well!

+1

seandogue2 years ago

I would simply use a nand gate rather than screwing around with an and and an inverter (not). Also, if you add an adjustable rc you can alter the frequency, as has been done for decades. Google it.

-max-2 years ago

To make that into a half-decent astable oscillator, I would add a Schmitt trigger and a integrator, like a RC circuit, so the output of the NOT goes into a "slow" RC circuit, which slowly charges up a capacitor until it triggers the Schmitt trigger, which, for argument's sake, say, is triggered HIGH at 3V, once HIGH, the input has to fall below 2V to turn it off.

Say the output of the NOT is HIGH, and the capacitor build up charge: 0V, 0.5V, 1V, 1.5V (it is actually not a linear increase like that, you can google RC time constant) then when it reaches 3V, the trigger is released, and the output going back to the input is finally HIGH. Then that changes the logic's almost instantly so that the output of the NOT is LOW. Then the capacitor charge fall's. Eventually it sag's down to below 2V, and the trigger is turned off, so the output is LOW. then the cycle repeats.

The frequency of oscillation is determined by the delay in the loop. That is determined by the value's for R, C, and the amount of change that has to occur, in our cause, between 2 and 3V. Precisely, the time it takes for the capacitor to charge to 3V, and discharge to 2V.

BTW, you *do* know you can simplify your circuit to just a NOT gate? The whole analysis I assumed the unconnected gate was HIGH, like you said, it is floating HIGH.

Its a very common way to make a rough oscillator. They aren't particularly stable like that. Its not much more work to make a crystal oscillator, sustained by logic gates though.

As Iceng comments, the LIMIT MAXIMUM frequency is the rise and fall time and transit delay through the gate, the minimum you can play with RC networks.