Preliminary Explanation/Precautions

Always refer to the Datasheets before performing any tests on an integrated circuit.

CMOS Operations:

An important thing to keep in mind is the 74HC595 (HC) is CMOS technology. The HC output signals are determined by VDD. Voltage levels range from 0 to VDD. A low level is anywhere between 0 and 1/3 VDD while a high level is between 2/3 VCC and VDD.

NEVER let CMOS inputs float.

NEVER apply an input without a power supply.

TTL Operations:

TTL integrated circuits operate from a 0-5 Vcc. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.

The 74HC595 is an 8-bit serial-in, serial or parallel-out shift register with output latches. The 595 is simply two registers. It operates similarly to a shift register but with one beneficial difference. The 595 has to ability to store 8 bits of data whenever necessary. Another important factor to keep in mind is that the 595 has a third output state, the Z state. The Z state allows the user to directly tie outputs together. The function of OE, or enable, not only determines if the contents of the storage register are enabled but also in a false state enters a High Impedance state(High Z) which in essence acts like an open. This Z state blocks any other output signals from damaging the IC.

Step 1: How We Are Going to Visualize the Characteristics of the 595

Summary

The following tests will be used to determine the operation of the 595. The DS (Data Serial) input will be used to shift 8 bits into the register. No data will be cascaded so the OE (Output Enable) input will be left in its true state (0). In this instance the data represented will be:

LSB 1 0 0 0 0 0 0 1 MSB

After all 8 bits have been successfully shifted in the STCP (Store Clock Pulse) will go to its true state (1) and latch the 8 bits.

Step 2: Assemble the Circuit

This is one way of utilizing the 595. The outputs (Q0-Q7S) are being monitored by a logic analyzer (Logic Port). I am using generated signal levels to operate all inputs: DS (Data Serial), MR’ (Master reset), OE’ (Output Enable), SHCP (Shift Clock Pulse) and STCP (Store Clock Pulse).

Note that I do not have the VCC and GND tied to anything. This circuit is merely a visual representation of how the circuit should be constructed. Always consult the datasheet for IC parameters and specifications.

Step 3: Waveform Generator Setup

The image above shows the

digital signals used to manipulate the 595. The signal characteristics are as follows:

SHCP- 500hz

DS- 1Khz

STCP- 1Khz

MR’- 1Khz

OE’- Constant Low(0)

Step 4: Function Diagram and IC Pinout

Step 5: Output Waveforms

Step 6: Master Reset

The MR’ input only clears the shift register. In order to see this action the STCP is taking a snapshot of the register on each rising edge of the SHCP clock.

The register is displaying 11111111 before the MR input goes low. After, all outputs Q0-Q7 change to a low voltage state followed by the DS input on each subsequent rising edge.

As shown in the waveforms and Figure 1 Q7S (Serial Data Out) clears asynchronously.