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Datasheet

-Materials:

-Leds

-Wires

For 1 Led, verilog code is:

module ledblink(clk,led);
input clk; output led; reg led;

reg[23:0] cnt;

always @(posedge clk) begin cnt<= cnt + 1'b1; led<=cnt[23];

end

endmodule

if you need more information about this tutorial, check my Blog

<p>That is one compact FPGA!</p><p>I use altera too. I have the max 10, and the cyclone 2.</p>

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