Introduction: Altera CPLD Max II Blink Led

Datasheet

-Materials:

-Leds

-Wires

For 1 Led, verilog code is:

module ledblink(clk,led);
input clk; output led; reg led;

reg[23:0] cnt;

always @(posedge clk) begin cnt<= cnt + 1'b1; led<=cnt[23];

end

endmodule

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Comments

author
CameronC32 (author)2016-02-19

That is one compact FPGA!

I use altera too. I have the max 10, and the cyclone 2.

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