Introduction: Basic of Verilog
Here i gonna explain about basic funadamental of writing programe in verilog .here i show that or operation done by me with design as well as test bench. try this on online programing websites.
Design: format for understanding
module npu (q,x,y); module portname (output,input);
output q; ..output ..
input x,y; input.......
or (q,x,y); gate operation(output,input)
endmodule finish module }
module testnpu; Write test with portname
wire q; Consider wire as input of design
reg x,y; Consider register as output of design
npu u1(.x(x),.y(y),.q(q)); define value
initial begin ( write this for read value as binary)
$monitor("%t %b %b %b",$time,x,y,q);
initial begin (write input which i learn in in truth table )
output: this output get from edaplayground.com
0 x x x
5 0 0 0
15 0 1 1
30 1 0 1
50 1 1 1
V C S S i m u l a t i o n R e p o r t
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Please be positive and constructive.