## Introduction: Basic of Verilog

HDl design:

Here i gonna explain about basic funadamental of writing programe in verilog .here i show that or operation done by me with design as well as test bench. try this on online programing websites.

** Design: ** format for understanding

module npu (q,x,y); __ module portname (output,input);__

output q; __..____output ..__

input x,y; **input.......**

or (q,x,y); __gate operation(output,input)__

endmodule __finish module }__

**Testbetch:**

module testnpu; __Write test with portname__

wire q; __Consider wire as input of design__

reg x,y; __Consider register as output of design__

npu u1(.x(x),.y(y),.q(q)); __define value__

initial begin __ ( write this for read value as binary)__

$monitor("%t %b %b %b",$time,x,y,q);

end

initial begin __(write input which i learn in in truth table )__

#5 x=0;y=0;

#10 x=0;y=1;

#15 x=1;y=0;

#20 x=1;y=1;

end

endmodule

** output: ** this output get from

__edaplayground.com__0 x x x

5 0 0 0

15 0 1 1

30 1 0 1

50 1 1 1

V C S S i m u l a t i o n R e p o r t

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