Introduction: Competitive Buzzer System

Picture of Competitive Buzzer System

The competitive buzzer system designed in this project operates similarly to the buzzer systems used in the Regional and National Science Bowl Competitions. This project was inspired by my involvement with my high school's science bowl team for three years. We have always had the desire to recreate the lock-out buzzer system with a 5-second and 20-second timer.

To give some background on the buzzer system, the science bowl buzzers are programmed to input a maximum of 8 players (with 8 separate buzzers). Once one buzzer has been pressed, the first person's buzzer will be lit to indicate which player receives the question. The rest of the players will be "locked out" which means their buzzers will not respond until the moderator resets the buzzer system.

After the moderator reads the questions, he will press a button to start the countdown timer that will be displayed on the seven-segment display. After a "toss-up" question, the moderator can press the right button to start the count down from 5 seconds. Meanwhile, after a "bonus" question, the moderator can press the left button to start the count down from 20 seconds. Once the timer reaches zero, a sound buzzer will indicate that the player has run out of time.

To reset the system and the count down timer, the moderator can press the center button. To reset the lockout mechanism and the player LEDs, the switches for player 1 and player 2 must be on low.

Step 1: Materials

Picture of Materials

You will need the following:

  • Basys3 board (or equivalent FPGA board)
  • Micro-B USB cable
  • Speaker (I used a passive speaker)
  • 2 wires
  • Software to implement on the FPGA (I used Vivado)
  • Competitive Buzzer System file

Step 2: Black Box Diagram

Picture of Black Box Diagram

The black box diagram shows the inputs and outputs that will be used in this buzzer system.

INPUTS:

player1, player2 These inputs are connected to two switches on the Basys3 board. For convenience, the leftmost and rightmost switches will be used.

reset The center button will be used to represent the reset button.

count_down_20_sec The left button will be used to represent the 20-second timer button.

count_down_5_sec The right button will be used to represent the 20-second timer button. To ensure that both the 20-second and 5-second timer starts, hold the button until the seven-segment display shows the timer.

CLK The FPGA board will generate a clock that runs with a frequency of 10 ns.


OUTPUTS:

speaker The speaker output is connected to an external buzzer or speaker. You will have to connect the speaker to the Basys3 board JA pmod ports. This step will be outlined below.

speaker_LED This output is connected to an LED on the center of the board, and will just indicate when the speaker output of the FPGA is high. You can use this for testing your external speaker. Note that some of the pmod ports might not function well, so you can try out different ones and use the LED to check if the speaker should be on.

SEGMENTS This output is connected to the eight individual segments on the seven-segment display, including the decimal point.

DISP_EN This output is connected to the four anodes on the seven-segment display.

player_LED This output is a 2-bundle signal that is connected to the LEDs above the player1 and player2 switches. The first player to flip their corresponding switch will be indicated by the LED. Note that both LEDs cannot be on simultaneously.


Step 3: Connecting the External Speaker

Picture of Connecting the External Speaker

To connect the external speaker to the Basys3 board, take your two wires and attach them as indicated in the above image. The white line connects the negative terminal of the speaker to the ground port on the board. The red line connects the positive terminal of the speaker to the JA10 pmod port on the board.

The constraints file is designed so that any port from JA1 to JA10 should work. However, some pins on the board are irresponsive, so if JA10 doesn't function, you may try the other ports.

Step 4: Structural Diagram

Picture of Structural Diagram

The image above shows the structural diagram of the competitive buzzer system including all the components that make up the main module. Their descriptions are as follows:

player_lockout_LED1 The player lockout LED component is a finite state machine that uses one-hot encoding. It has four inputs: player1, player2, reset, and CLK. It contains a 2-bit bundle output player_LED. The inputs and outputs of the player_lockout_LED1 component are all directly connected to the identically-named inputs and outputs of the main module.

buzzer_tone1 The buzzer component is based on this code posted on a forum

https://stackoverflow.com/questions/22767256/vhdl-... However, it was modified to output a continuous sound with a frequency of 440 Hz (A note). The enable input is connected to a buzzer_enable signal which is an output of the down_counter_FSM1 component.

clk_div1 The clock divider component is a modified version of Professor Bryan Mealy's clock divider provided on PolyLearn. It slows down the clock so the output period is 1 second.

down_counter_FSM1 The down counter is an FSM designed to count down to zero. The two possible start times are 20 or 5 which is chosen by the user input. It outputs '1' when the timer has reached zero to indicate that time has run out. This output acts as an enable for the buzzer tone component. The counter also outputs an 8-bit bundle signal that sends an 8-bit BCD that is sent to the segment decoder. Another output is the counter_on which is also connected to the valid input on the segment decoder.

sseg_dec1 The seven-segment decoder component is provided on PolyLearn and was written by Professor Bryan Mealy. It uses a BCD input provided by the down_counter_FSM1, and outputs the decimal equivalent on the seven-segment display. When the counter is on, then the valid input is high. This allows the decoder to display the decimal number on the seven-segment display. When the counter is off, then the valid input is low. The seven-segment display will then only show four dashes.

Step 5: Finite State Machine (FSM) Diagram

Picture of Finite State Machine (FSM) Diagram

The sensitivity list for the finite state machine includes player1, player2, reset, and the clock. The FSM output is a 2-bit bundle player_LED connected to two LEDs on the Basys3 board. The Finite State Machine shows the following three states:

ST0 is the start state. In this state, the two LEDs are turned off. The FSM will remain in this state if both player1 and player2 are low. An asynchronous reset also sets the state to ST0. When the player1 switch is set to high, the next state will be ST1. If the player2 switch is set to high, the next state will be ST2.

ST1 is the state for which player1 LED is on. The FSM will remain in this state for any input. This means that even when the player2 switch is set to high immediately after the player1 switch is high, it will remain in ST1. Only the asynchronous reset can set the next state to ST0.

ST2 is the state for which player2 LED is on. Similar to ST!, The FSM will remain in this state for any input, even when the player1 switch is set to high immediately after the player2 switch is high. Again, only the asynchronous reset can set the next state to ST0.

Comments

DIY Hacks and How Tos (author)2017-12-10

Cool project. You should enter this into the Arduino contest that is currently running. It is open to all microcontroller projects.

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