##This is the most clicked, popular link in Google for VHDL implementation of CORDIC ALGORITHM##

At present time, many hardware efficient algorithms exist, but these are not well known due to the dominance of software systems over the many years. CORDIC is such an algorithm which is nothing but a set of shift and add logics used for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. Thus by just using simple shifters and adders we can design a hardware with less complexity but power of DSP using cordic algorithm . This is the algorithm used in calculators etc.

## Step 1: VHDL and Modelsim

Here the cordic algorithm is implemented using VHDL to generate a sine wave and cose wave . The code is synthesizable on FPGA. Modelsim is used to simulate the design and the test bench .

## Step 2: VHDL Code for the Design and the Test Bench

---- Guidelines ----

Simulating cordic_v4.vhd - The Design

(1) The input is angle in 32 bits + sign bit ; it can process any angle from 0 to +/-360 degree with input precision of 0.000000000233 degree. When giving input -> MSB is the sign bit and the rest 32 bits represent magnitude .

(2) The output of the design is its sine and cos value in 16 bits + sign bit .ie; with precision 0.00001526. Please note that the output is displayed in 2's compliment form if the respective sine or cos value is negative.

Simulating testb.vhd - Test Bench For The Design

(1) After two steps of simulation pull reset to '1' and " run all ".

(2) In simulation window set the radix of sin and cos signals as decimal and format > Analog ( automatic ).

(3) Zoom out to see the waveform properly.

## Step 3: Files Attached

(1) cordic_v4.vhd - Design .

(2) testb.vhd - Test bench for the design .

Designed by

Mitu & Roshan

India

contact for queries : iammituraj@gmail.com

## Step 4: Mini-Cordic IP Core - 16 Bit

Limitation of the above implementation is

- Slower because of doing computations in a single clock cycle.

Mini-Cordic IP Core - 16 Bit is

- Pipelined architecture

- Faster - FPGA proven design synthesised upto 100 Mhz clock.

- More area optimised , Lesser hardware.

- Suitable to be integrated with processors.

Only downside is lesser resolution compared to the previous one.

Please check the documentation attached with. Thank You !

contact : iammituraj@gmail.com

<p>Hi. What is the password for the Zip file ?</p>
<p>contact in mail.</p>
<p>Hello. Could you send me the password for the Zip file, please?</p>
<p>what is the code the unzip the file and thanks </p>

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