DIY CMOS RAM Memory

Step 4 How It Works

This version uses a conventional Data Latch (D-Latch). Its basically a shortcut version of the Master-Slave D-Flip Flop. It uses 4 NAND gates to operate. When the clock goes high, the Q output will follow any changes from Data. When the Clock goes low again, the bit is latched. Now the Q output will not change states, even when Data does.

Comments

[parukboy]

This looks very similar to a negative edge flip flop

[Teslaling]

Thats because it IS very similar. The main differences are that this is a latch not a flip flop, and that it is positive edge triggered!

[parukboy]

Thanks for the help. The rest ill figure out.

[parukboy]

I don't understand why 2 latch circuits are needed instead of 1, it does the same thing does it not ?

[Teslaling]

The 2 latch circuit is a master-slave flip flop. At first I had the same thought, but it is so that the change in Q doesnt appear until the falling edge of the clock signal, instead of the rising edge. Its commonly used in shift registers because if the change in Q occurs when the clock is high, then that signal will get shifted the whole way down to the most significant bit. If the change in Q doesn't occur until the falling edge, then the data will stay in that flip flop until the next clock cycle.

[parukboy]

How do you set Q as 1 ?

[Teslaling]

You have to do 2 things, 1) you have to set DATA as 1 and 2) you set the clock high, then back low. It will latch the Q as 1.