DIY CMOS RAM Memory

Step 5 The NAND Gate

The basis of this circuit is the NAND gate. Its function is the not of A and B (~A*B):

A    B    Y
0    0    1
0    1    1
1    0    1
1    1    0

It requires 4 MOSFET to operate, 2 P-channels and 2 N-channels in the configuration below. The P-channel FETs are in parallel, but the N-channel FETs are stacked up, in a "Totem Pole" configuration. If either A or B is low, then current can flow through one of the the P-channel FETs, making Y logic 1. This is true to the truth table. If both A and B are high, then the P-channel FETs turn off and both N-channel FETs turn on, making Y logic 0. As true to the table.