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Step 2What's Going On?
The basis of the circuit is the SR Flip Flop. This flip flop circuit uses 2 inputs, Set and Reset, to control 2 outputs, Q and ~Q (not Q). When the Set line goes high, Q will go high and stay high even after Set goes low. If, however, Reset goes high, then Q will go low and ~Q will go high.
Now the question becomes how do we make all of this happen with only one input? We do this by connecting the data line to the Set input and connecting it to the Reset line through an inverter.
So far, when Data is high, Set is high and Reset is low so Q is high. If Data goes low, then Set goes low and Reset goes high making Q go low and ~Q go high. Now we have another problem. The register changes states when the Data does, it doesn't latch like we want it to. How do we fix this? By adding a Write Enable. We can do this by adding a gated buffer. It acts as a switch so if the switch line goes high or low the buffer will either turn off or on, respectively. Now, even when the data line can change states, the data can remain the same.
Now the question becomes how do we make all of this happen with only one input? We do this by connecting the data line to the Set input and connecting it to the Reset line through an inverter.
So far, when Data is high, Set is high and Reset is low so Q is high. If Data goes low, then Set goes low and Reset goes high making Q go low and ~Q go high. Now we have another problem. The register changes states when the Data does, it doesn't latch like we want it to. How do we fix this? By adding a Write Enable. We can do this by adding a gated buffer. It acts as a switch so if the switch line goes high or low the buffer will either turn off or on, respectively. Now, even when the data line can change states, the data can remain the same.
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D = 1
WE = 1
Q will = 1
THEN
D = 0;
WE = 0
Q will = 1 because when R & S = 0 , Q = 1
BUT
D = 0
WE = 1
Q will = 0
THEN
D = 1;
WE = 0;
Q will = 1 because when R & S = 0, Q = 1
Or have I gone wrong somewhere ?
When:
D = 1,
WE = 0,
Then:
R = 0,
S = 1,
Q = 1
When:
D = 1,
WE = 1,
Then:
R = last state,
S = last state,
Q = last state
When:
D = 0,
WE = 0,
Then:
R = 1,
S = 0,
Q = 0
When:
D = 0,
WE = 1,
Then:
R = last state,
S = last state,
Q = last state.
When R & S are 0, then Q becomes latched on the last signal input. Remember also that the WE does NOT make the signal 1 when its 1, it lets the data signal pass, so it the data is 0 then the output of the gated buffer is 0.
I hope that this clarified things for you :)