Introduction: Energy Conservation: Smart Light for Auditorium
Leaving the lights on when no one is the room is a crime almost everyone is guilty of. Well what if you created a smart light, which would turn on when multiple people left the room, and off when they have all left. That is exactly what this project creates, but with the capability of functioning throughout multiple rooms. Utilizing a Field Programmable Gate Array (FPGA), a circuit board, an Op-Amp, some resistors, a photodiode, phototransistor, and a whole lot of logic you can do just that.
Why this project is worth your time: With the continuous pressure to save energy and create better optimized systems this project is a fun and involved method of getting your hands dirty with practical circuitry applications and coding experience with VHDL. You will gain insight into a practical application of Finite State Machines (FSM) using VHDL, taking a blackbox diagram and bringing it to life, and working with circuit boards to use an Op-Amp as a comparator.
Project Members: Brian Arbiv, Chris Audi, Zach Barram, Cameron Simpson
Special thanks to:
1) Digilent Inc for providing the Basys3 Master XDC File for Vivado and the reference manual for the FPGA.
basys 3 webpage: https://store.digilentinc.com/basys-3-artix-7-fpg...
and Master XDC File for Vivado,
reference manual: https://reference.digilentinc.com/_media/basys3:b...
2) Digital McLogic Design by Bryan Mealy at Cal Poly
3) shutterstock for providing the cover photo: https://www.shutterstock.com/pic-172769996/stock-...
4) Professor Andrew Danowitz for providing advice
5) Op- Amp Comparator information provided by Electronics Tutorial: http://www.electronics-tutorials.ws/opamp/op-amp-...
Step 1: Materials
1) Vivado software, provided free from Xilinx. A step by step guide can be seen in the Vivado Installation file.
2) A Digilent Inc. Basys3 board
3) Basys3 Master XDC file
3) Six photodiodes and Six phototransistors
4) 50 ft of 16 gauge wire
5) A breadboard
6) Three LM 358 Dual Operational Amplifiers
7) Resistors: Various types that depend on the LED's
8) Power Supply
9) 3 LED's (any color)
Step 2: Non-Inverting Comparator Op-Amp
While it may sound like a mouthful, the Op-Amp serves to convert the output voltage from the photodiode branch of the circuit into either a high value (5V) or a low value (0V). The Op-Amp output will be sent to the FPGA to interpret into the logic of the design. This is the initial input that the design utilizes to base the function of the logic on.
The Op-Amp functioned through the use of an IR photodiode and IR LED. The LED would continuously send a pulse outward. When an object (a person) would step in the path of the pulse it would reflect off that object and enter the photodiode. When the photodiode received an impulse it would lower its resistance and allow a potential to be created across it and send a current through the circuit.
During the creation of our project, we used a variable resistor as shown in the image to determine the resistance values to use based on the base state voltage (no IR feedback) from the photodiode branch. It was determined that we needed a 2k resistor in series with a 16Ω resistor to achieve this goal. This will vary based on the photodiodes used, so be sure to test your sensors with a potentiometer prior to using
When the circuit received that current it would travel to the 16Ω resistor and be compared by the Op-Amp at its inverting and non-inverting terminals. When Vin is greater than the reference voltage, the Op-Amp will saturate towards the positive supply rail. When the Vin is less than V reference the Op-Amp will saturate towards the negative supply rail, which would output a voltage of 0V. If the potential within the 16Ω resistor was greater than the reference voltage the Op-Amp would output a voltage. This output voltage is then sent to the FPGA and translated from an analog signal to digital. The interpreter processed this information.
Step 3: The Blackbox Diagram ( We Detail the Utilization of Each Component Here)
To start implementing the project, the required entities had to be identified: Interpreter, Controller, Multiplexor, Adder, Register, and Comparator. The red pathway in the image shows the connection of the components during one clock cycle in the design.
1) Interpreter: We need a process of taking our analog inputs and convert them to digital values so that the FPGA could do something with this data. The logic that analyzes the incoming data was named "Interpreter". We used three interpreters in our project so that we could model three rooms, and keep track of all the people entering and leaving each one. Each interpreter would consistently output a value of 0 until a person walked into the room and then output a value of 1 then shift back to 0 at the next clock cycle.
2) Controller: To make sure that all components in the project would perform there function when they needed to we created a controller. The controller made sure that all of the mux's would switch their position at the same time so that all of the necessary data pertaining to each "room" would be processed at the same time. In simpler terms the controller was used to make sure that the data from room one did not get mixed in with the data of room two.
3) Multiplexor (Mux) : Four mux's were used between each module. The modules that performed calculations and stored the data had a mux before each one of them so that the incoming data would be from the correct "channel" and not get mixed in with other "channels". The controller controlled the muxes so that they would change positions at the same time to allow for data to be passed through each module.
4) Adder: The adder would take the value that was stored in each 8-bit register at a time and add it to the incoming values from the interpreter. Those values would be then be passed through a mux and fed back into the same register so as to store the new value.
5) Register: An 8-bit register was used to store the output value from the adder. The reasoning behind 8 bits was that it would allow for a very large amount of people to be counted before going over the limit able to be stored. The highest amount of people in each room possible was 255. The 1-bit register was used to hold the output of the comparator. Since the comparator is only concerned with the value being greater than zero it could only output two values; greater than zero and equal to 0. This only requires 1-bit to represent these two possible values.
6) Comparator: The comparator utilized was hardwired to compare the receiving values with 00. The reasoning for this is that we are only concerned with the room being empty. As long as the incoming value from the register is greater than zero then we know that people are in the room.
Step 4: The Interpreter (FSM)
We need a process of taking our analog inputs (the data from the Op-Amp comparator) and convert them to digital values so that the FPGA could do something with this data.
Each interpreter would consistently output a value of 0 until a person walked into the room. When someone walks in the room they will hit the first sensor and then the second sensor, the interpreter will then output a value of 1 then shift back to 0 at the next clock cycle. If a person leaves the room the interpreter will output a -1 to indicate a person leaving the room. If either sensor gets triggered without the other, the circuit will wait for a second and then reset in order to avoid a false reading. If the interpreter sends a -1 when the registers are zero, the registers will just stay zero.
Another feature to avoid conflicts with bad readings is the timer that indicates whether a second has passed in between sensor readings. If the second sensor isn't hit prior to a second passing, the interpreter will reset to begin another reading.
This was implemented using behavioral modeling in VHDL using case statements. With each clock cycle, the current state of the FSM would determine the next state, which would transition at the beginning of the following cycle. Inside of the case state is also the assignment of what values will be sent to the data out, as well as output signals to the timer.
The output data is sent to the adder unit, which will add the previous register value of that row with the output of the interpreter.
Step 5: Remaining Logic
Rather than implementing the comparator, adder, and registers as singular components, they were all implemented using behavioral modelling in a single component. The Logic.vhd file included incorporates all of these concepts into the design.
Step 6: The Comparator
The comparator utilized was hardwired to compare the receiving values with 00. The reasoning for this is that we are only concerned with the room being empty. As long as the incoming value from the register is greater than zero then we know that people are in the room. In this project we will be using behavioral logic to implement this comparator.
Step 7: The Controller
The controller is actually quite simple, it just changes its value based on the rising edge of the clock. Its initial value is zero and it gets incremented each time the clock hits a rising edge, it then resets after reaching the value of two. So first it is zero, then at the first rising edge of the clock it gets incremented to one. Then at the next rising edge of the clock the value increases to two. After that the value is reset back to zero at the next rising edge. This value is used as the selector signal in the MUXes and decoders, to determine which room is gathering data at a time. In the VHDL, the controller is essentially two nested if statements, the first responds to the rising edge of the clock. The second if statement asks if the count of the controller if less than two. If both of these conditions are met then the controller increments count by one.
Step 8: The Adder and Main Storage Registers
The adder will take the values from the interpreter and from the registers. Which interpreter and which register it uses will be determined by the controller. If the interpreter is sending a negative one to the adder when the value on the register is already zero then nothing happens, the register will keep the zero value. The result of the adder will be stored in the register that sent the original stored value to the adder. Each register stand in for the current state of a room, it hold the number of people in each room. The VHDL for this is a behavioral model in the form of case statements. Essentially, the case statements respond to the change in the controller's count value, with this it assigns the correct signal to variables which are then fed through a adder. This adder output is then saved to a register, which register depends on the count.
Step 9: Single Bit Light Registers
The second set of registers are only really used to control the lights in the room, they store the value coming from the comparator. If they are no people in the room these registers will hold a value of zero, if some one is in the room it will hold a value of one. If they are holding a one then the lights will be on and if they are holding a zero then the lights will be off. The VHDL for this is contained within a case statement, the VHDL that get executed depends on the count of the controller. Essentially, in this set of case statements the variables are assigned to the output signals.
This second set of registers is necessary because each clock cycle means that the controller is connecting to different light sets. We need to store whether or not the light is on, that way the light will stay on even when that row is not accessed in the logic.
Step 10: Connecting Input/Output
The output from the sensor circuits is fed into the JA PMOD ports on the FPGA, with the ground wire tied to the ground of the sensor circuits. The light outputs were sent from the JB PMOD ports, with the ground lines similarly tied to the ground of the sensor circuit. Attached is the constraints file we used, however the individual ports can be rearranged with no obstruction to the functionality of the design.
Once this is complete, your automated lights should count how many people come into a row, and ultimately save you a fortune on your electric bill!
We have a be nice policy.
Please be positive and constructive.