Step 13: Control Matrix
The control matrix of a computer tells each individual part when to take input and output its value. There are multiple states of each operation in a computer. These states are triggered by a type of counter called a ring counter. A ring counter only has one bit high at a time and cycles through its outputs consecutively. For instance, if a ring counter has 4 outputs it will first have its first output active. At the next clock pulse it will set its second output high (and the first low). The next clock pulse will advance the bit one output higher and so on. These stages are called T states. The computer in this Instructable uses 6 T states for the operation of one command. The first three T states are what is called the fetch cycle in which the current instruction is fetched and placed into the instruction register. The program counter is also incremented by one. The second set of three T states depends on what OP code is fed into the control matrix from the instruction register. The T states are as follows:
T1: The contents of the program counter are transferred into the memory address register. (Address State)
T2: The program counter is incremented by one. (Increment State)
T3: The addressed byte in the program memory is transfered into the instruction register. (Memory State)
T4: Dependent on what command is being executed.
T5: Dependent on what command is being executed.
T6: Dependent on what command is being executed.
There are two primary ways to create a control matrix: using discrete logic and using ROM's. The ROM method is the easiest and most efficient. Using discrete logic involves designing a massive logic schematic that will output the correct control words for your computer based on an OP code input. ROM stands for read-only-memory. There are several types of ROM's that you can consider for use in your build. For my computer I originally used EEPROM (electronically erasable programmable ROM) but then shifted to NVRAM (non-volatile random access memory) after the EEPROM chips failed to write. I do not recommend NVRAM as it is meant for random access memory and not permanent storage. EEPROM is the most efficient solution in my opinion.
The control matrix will have three ROM chips each having at least 32 addresses of 8 bit storage (as well as the timing and counting elements). The binary word that is sent out from the control matrix is called the control ROM and contains all of the control bits for every component of your computer. You want to be sure to organize the control bits and know their order. For no operation you want a control word that renders every part of the computer inactive (except the clock of course). The control word for the computer described in this Instructable is 16 bits in length and is stored in two of the control ROM chips. The first three addresses of the control ROM chips hold the control words for the fetch cycle. The rest of the addresses on the chip hold the control words in pairs of three for each OP code. The third ROM chip holds the memory location for the start of the control word sequence for each OP code and is addressed by the OP code itself. For instance, in my computer if you give the control the OP code 0110 it will output binary 21, which is the address of the start of the JMP command. There is an 8-bit counter in between the OP ROM and the control ROM's that counts from 0-2 (first three T states) then on the third T state loads the address outputted by the OP ROM and counts from that position until the T1 state clears the counter again. The ring and binary counter for the control matrix are controlled by an inversion of the clock pulse so that control words are present when the rising clock pulse goes to the elements of the computer. The entire process in order is as follows:
1.) T1 state clears the counter to 0, the control word stored at 0 is sent out
2.) The clock goes high and the address state takes place
3.) The clock goes low and in turn the control counter increments and control word 1 is sent out
4.) The clock goes high and the increment cycle takes place
5.) The clock goes low and the control counter increments to 2, control word 2 is sent out
6.) The clock goes high and the memory state takes place and the OP code arrives at the instruction register, T3 is also active which means on the next low clock pulse the OP control address will be loaded
7.) The clock goes low and loads the counter with the address for the first of the three control words for the given OP code
8.) T4, T5 and T6 execute the OP code
9.) T1 resets the counter, the process continues until a HLT OP is received. The HLT command stops the clock.