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Step 3Thoughts about Architectures
The "architecture" of a microcontroller refers to the philosophy of the internal implementation, sort of. It includes details like how many "registers" there are, and how "general purpose" those registers are, whether code can execute out of data memory, whether the peripherals are treated like memory, registers, or yet something else, whether there is a stack and how it works, and so on.
You will hear people talk about how some architectures are better than others. I suppose this is true. But I'm going to claim that it is largely irrelevant for the typical hobbyist. If you wish to avoid the architectural quirks of a particular family of microcontrollers, you can use a high level language. If you're willing to program in assembler, you're at a level of interest where learning and overcoming the quirks is party of the stuff you should be learning. Besides, we're not talking here about evaluating some new architecture that some company is proposing. All of the chips I mention in this instructable have been around long enough that they've proven that their architectures are good enough for MANY real applications.
Here are some architectural "features" you may read about and some explanation of what they mean.
CISC/RISC. Complex Instruction Set Computer. Reduced Instruction Set Computer.
In the old days, CPU designers were getting clever and wanted their CPUs to support high-level language features in hardware, leading to cobol-like string manipulation instructions that accepted arguments in blocks of 8 registers. IIRC, it was Berkeley and IBM who noticed that compiler writers didn't really know how to USE such complicated instructions from a compiler, the amount of silicon real estate used by these instructions was getting large, and in fact the hardware implementation sometimes wasn't as fast as doing the same thing in software anyway. So they said "I bet we can make the CPU go a lot faster if we leave out these complex instructions and dedicate the silicon to more registers or cache memory or something", and thereby invented the RISC CPU. Nowadays "RISC" is widely used by marketing departments to mean "we don't have very many instructions", even if the rest of the architecture isn't very much like the original RISC researchers had envisioned.
Harvard Architecture.
In a Harvard architecture, the instruction memory and the data memory are separate, controlled by different buses, and sometimes have different sizes. For microcontrollers, the instructions are usually stored in "read only" memory, and data is in RAM or registers. An example is the
PIC microcontroller, where instructions are in 12, 14, or 16 bit wide flash, and data is in 8bit
wide RAM.
Von Neuman Architecture.
In a von Neuman Architecture, data and instructions share memory space, so you could do things like dynamic compilation to generate instructions in RAM and then execute them. The TI MSP430 is an example of a von Neuman architecture.
Accumulator based
In an "accumulator based" architecture, there is usually one "special" register where most of the actual computation (math, logic, etc) occurs. Some effort has to be spent to get operands into the accumulator and results back out to where you need them. The opposite is a processor with "general purpose" registers, where any of several registers can be used for math/etc.
Load/Store
A load/store architecture typically means that operands to ALU operations have to be in registers, so that you have to load them from memory beforehand and store them back when operations are complete. The opposite typically allows operations between a register or
accumulator and a memory location directly. RISC architectures tend to be load/store, since a lot or the CISCness of CISC processors shows up in implementing complex "addressing modes" for accessing the memory operands. In a RISC architecture, all that complexity only has to be implemented in the load and store instructions (if at all.)
Registers
Memory Mapped I/O
You will hear people talk about how some architectures are better than others. I suppose this is true. But I'm going to claim that it is largely irrelevant for the typical hobbyist. If you wish to avoid the architectural quirks of a particular family of microcontrollers, you can use a high level language. If you're willing to program in assembler, you're at a level of interest where learning and overcoming the quirks is party of the stuff you should be learning. Besides, we're not talking here about evaluating some new architecture that some company is proposing. All of the chips I mention in this instructable have been around long enough that they've proven that their architectures are good enough for MANY real applications.
Here are some architectural "features" you may read about and some explanation of what they mean.
CISC/RISC. Complex Instruction Set Computer. Reduced Instruction Set Computer.
In the old days, CPU designers were getting clever and wanted their CPUs to support high-level language features in hardware, leading to cobol-like string manipulation instructions that accepted arguments in blocks of 8 registers. IIRC, it was Berkeley and IBM who noticed that compiler writers didn't really know how to USE such complicated instructions from a compiler, the amount of silicon real estate used by these instructions was getting large, and in fact the hardware implementation sometimes wasn't as fast as doing the same thing in software anyway. So they said "I bet we can make the CPU go a lot faster if we leave out these complex instructions and dedicate the silicon to more registers or cache memory or something", and thereby invented the RISC CPU. Nowadays "RISC" is widely used by marketing departments to mean "we don't have very many instructions", even if the rest of the architecture isn't very much like the original RISC researchers had envisioned.
Harvard Architecture.
In a Harvard architecture, the instruction memory and the data memory are separate, controlled by different buses, and sometimes have different sizes. For microcontrollers, the instructions are usually stored in "read only" memory, and data is in RAM or registers. An example is the
PIC microcontroller, where instructions are in 12, 14, or 16 bit wide flash, and data is in 8bit
wide RAM.
Von Neuman Architecture.
In a von Neuman Architecture, data and instructions share memory space, so you could do things like dynamic compilation to generate instructions in RAM and then execute them. The TI MSP430 is an example of a von Neuman architecture.
Accumulator based
In an "accumulator based" architecture, there is usually one "special" register where most of the actual computation (math, logic, etc) occurs. Some effort has to be spent to get operands into the accumulator and results back out to where you need them. The opposite is a processor with "general purpose" registers, where any of several registers can be used for math/etc.
Load/Store
A load/store architecture typically means that operands to ALU operations have to be in registers, so that you have to load them from memory beforehand and store them back when operations are complete. The opposite typically allows operations between a register or
accumulator and a memory location directly. RISC architectures tend to be load/store, since a lot or the CISCness of CISC processors shows up in implementing complex "addressing modes" for accessing the memory operands. In a RISC architecture, all that complexity only has to be implemented in the load and store instructions (if at all.)
Registers
Memory Mapped I/O
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