Introduction: Nexys 4 DDR (FPGA) Based Lock-in Amplifier
Lock-in amplifier is an instrument, that measures amplitude and phase shift of periodic signals precisely. Instead of signal filtering to measure known frequency, it uses properties of sine function to achieve very high Q factor (selectivity). This makes it ideal in many applications where small amplitude signal or high noise is present.
As the main parts of Lock-in amplifier includes signal processing operations, it is good idea to use FPGA to implement it. FPGAs can be very fast and accurate. If we add some converters to mix analog and digital domain, high precision Lock-in can be developed.
In this tutorial we will use Digilent's Nexys 4 Development Kit with Xilinx Artix 7 FPGA. This IC is quite big programmable device with integrated DSP blocks, which allow us easy implementation.
Step 1: Implementation Understanding
In the picture there is a general schematic of lock-in amplifier. As you can see, the input signal is multiplicated twice, by the reference sine and by the reference cosine. Frequencies of references must be equal to the input signal frequency. For best, Lock-in has its own internal reference generator, so we will also implement such a module in FPGA.
Step 2: Vivado Project Setup
After you installed Vivado SDK from Xilinx, you have to Create a new project. Follow the steps:
1. Click 'Create New Project' icon
2. click Next and point the directory and name of your project
3. choose 'RTL Project'
4. click 'Add files', choose all files provided and change 'Target language' to VHDL from the list
5. find xc7a100tcsg324-1 on the list
Your window after these steps should look like in the image.
Step 3: Code Synthesis and Bistream Generation
After you succesfully prepared your project, you can generate a bitstream file to configure your FPGA. To do this, click on 'Generate bitstream' button down on the left side. All needed substeps will do automatically.
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