Introduction: Nexys 4 DDR LED Strip Audio Spectrum

Picture of Nexys 4 DDR LED Strip Audio Spectrum

Project description

The project uses the Digilent Nexys 4 (DDR) on-board microphone to capture the environment sound. The audio signal is shown both in the time domain and frequency domain (spectrum) on a VGA display. The spectrum is also shown on a 30 color LED strip. See the movie.

Required components

Project files

The project works with either Nexys 4 or Nexys 4 DDR boards from Digilent. These boards use the same Xilinx Artix 7 FPGA (XC7A100T-1CSG324C) and a very similar schematic. However, the pin assignment is different for the two boards. For this reason, the source files of the project are similar, except for the .xdc file, which is specific to each board. The compiled files (.bit or .bin) are also board specific.

  • The Nexys4DdrSpectralSources.zip file includes:
    • The source files of the project
    • The .tcl file needed to automatically build the project
    • A readme.txt file describing the procedure to build the project
    • The .bit and .bin files for programming the FPGA, respectively the SPI flash on Nexys4 or Nexys4DRR boards.

Step 1: Installing and Using Vivado

The Vivado WebPack can be downloaded from here.

Project 1.1: Introduction to Digital Engineering and FPGA Boards shows how to install Vivado, create a project, compile and download to the FPGA file.

Step 2: Functional Details

The PDM signal of the microphone is filtered and decimated to a 48KHz, 16 bit audio sample string.

The audio sample string is stored in a Time Domain block RAM for VGA representation.

An identical copy of the audio string is stored in a second block RAM for feeding the FFT core. The FFT output data is also stored in a Frequency Domain block RAM.

Both Time Domain and Frequency Domain block RAMs feed the VGA image controller. The time signal is shown on the upper half and the spectrum on the lower half of the screen.

The Frequency Domain block RAM also feeds the 30 LED string controller. Each LED in the string is assigned a 47Hz frequency bin (total frequency range 47Hz to 1.4kHz). Each LED has a constant color, from RED (corresponding to lowest frequency in the spectrum) to VIOLET (highest frequency). The intensity of each LED shows the momentary power of the assigned frequency.

The audio output of the Nexys 4 (DDR) board generates a reverberated version of the audio input signal.

The switches of the Nexys 4 (DDR) board select:

  • FFT transform sensitivity - sw(2:0):
    • “000” = lowest sensitivity
    • “111” = high sensitivity
  • LED displayed pattern – sw (15:14)
    • “00” = FFT spectrum,
    • “01” and “10” = Rainbow
    • “11” = constant color (yellow)

Step 3: Building the Experiment HW

Picture of Building the Experiment HW
  • Connect the Nexys 4 to:
    • the VGA display
    • the PC, via the USB cable
    • the WS2812 addressable LED strip, via 3 male to male wires on connector JC.
      • GND (white wire) to JC5
      • Vcc (red wire) to JC6
      • Data (green wire) to JC4

Step 4: Download the Configuration File to the FPGA

Picture of Download the Configuration File to the FPGA
  • Unzip Nexys4DdrSpectralSources.zip in a convenient folder
  • Switch on the PC, VGA display and Nexys 4(DDR) board
  • Launch Vivado
  • Click on “Open Hardware Manager”
  • Click on “Open a new hardware target”
    • Click Next on the two next windows
    • In the “Select Hardware Target” make sure you select the Nexys 4 (DDR) board (only if you have more Xilinx FPGA boards connected). Click “Next”
    • Click “Finish”
  • Click on “Program Device” and select”xc7a100t_0”
  • Navigate to the appropriate .bit file:
    • /Nexys4DdrSpectralSources/bin/Nexys4/TopNexys4Spectral.bit for a Nexys 4 board or
    • /Nexys4DdrSpectralSources/bin/Nexys4DDR/TopNexys4Spectral.bit for a Nexys 4 DDR board
  • Click “Program” and wait for the Done LED to turn ON.
  • Speak or apply sound to the board. The LCD display shows the time and frequency domain representation. The LCD strip shows the spectra of the audio signal. Play with the Nexys4 (DDR) switches, as explained in Step 2.

Step 5: Re-build the Vivado Project. Understand, Edit, and Modify It.

Picture of Re-build the Vivado Project. Understand, Edit, and Modify It.

In Nexys4DdrSpectralSources.zip, open the readme.txt file describing the procedure to build the project. Follow the steps to re-build the Vivado project from the provided sources.

Important note: As shown in the readme.txt, the project is ready to compile for a Nexys4 DDR board. If you want to compile it for a Nexys4 board, remove from the project constrains the file called Nexys4DDR_Master.xdc and add instead the file called Nexys4_Master.xdc. (\src\constraints).

Analyze the structure of the project:

  • TopNexys4Spectral - Produces a flgStartAcquisition pulse every 100ms, to initiates a computation cycle. Instantiates:
    • clkGenInst - a clock generator Vivado IP core. Uses an 100MHz input clock and generates:
      • 25MHz clock for the VGA controller
      • 4.8MHz for the audio demo component.
    • Audio_demo_inst - the Digilent Audio demo project, as published and described here. Produces 16 bit, 48KSPS audio signal.
    • Inst_fftBlock - computes the FFT of the audio_demo output signal.
      • Instantiates:
        • TimeBlkMemForFft - Vivado IP core: 8 bit, 1024 samples dual port RAM, to store audio signal and provide it to the FFT core.
        • FftInst - Vivado IP core: Computes the FFT of the signal stored above.
      • ResetStateMachine initializes the FFT core.
      • TimeCounter indexes the samples in the TimeBlkMemForFft.
      • TimeAcqSync synchronizes the TimeCounter with the flgStartAcquisition and audio signal rising edge at level zero.
      • FftLoadCounter indexes the samples to load the FFT IP core (time samples).
      • FftUnloadCounter indexes the samples to unload the FFT IP core (frequency domain samples).
    • Inst_VgaCtrl – generates the VGA sync signals as well as the vertical and horizontal counters to locate the current displayed pixel.
    • Inst_ImgCtrl – generates the image of the VGA display.
      • Instantiates:
        • TimeBlkMemForDisplay - Vivado IP core: 8 bit, 1024 samples dual port RAM, to store audio signal and provide it to the VGA display. Synchronized clone of TimeBlkMemForFft.
        • FreqBlkMemForDisplay - Vivado IP core: 8 bit, 1024 samples dual port RAM, to store audio frequency domain samples and provide it to the VGA display.
    • inst_LedStringCtrl – builds the image to display on the LED strip.
      • Generates the color definitions of the rainbow.
      • Stores the values of the first 30 frequency domain samples.
      • Combines the two infos above to generate the frequency dynamic show on the LEDs.
      • Reads switches to select static or dynamic image on the LEDs.
      • Instantiates:
        • U1 - led_controller = led controller
          • gets color data for each LED in the strip.
          • Combines the three colors for each LED
          • Combines the 30 LED colors info in a single bit string.
          • Encodes the bit string as a NRZ code to drive the LED strip.

Modify the project upon your convenience. Feel free to use it entirely or parts of it in your projects.

Comments

tomatoskins (author)2015-03-18

I think that a video of this would be awesome to see!

I added the video.

I cannot see it embedded in the web page. However, I can download it and see it with my media player.

About This Instructable

5,231views

15favorites

License:

Add instructable to: