In this project, we are going to examine the delay in combinational circuits. We are going to tell the simulator of the delay of each gate in Verilog and simulate the circuits to see how delay can affect the behavior of a combinational circuit.

Before you begin, you should:

-Have the Xilinx® Vivado WebPACK™ installed.

-Have your FPGA board set up.

-Be able to derive a logic equation from a truth table.

-Be able to describe logic functions using Verilog HDL and implement them in FPGA.

-Be able to write test bench and use the Xilinx® Vivado Simulator.

While all the basic theory will not be covered here, these links can provide you with the relevant background you will need:



Step 1: Implement the Circuit in Verilog

In this project, we are going to implement a circuit in Verilog and simulate it, taking delay into consideration. The circuit schematic is shown in Fig. 1 above, and the delay of each gate is marked in red.

The circuit takes three inputs (A, B, C) and one output (X), so the declaration of the module goes as follows:

1 module CombCirc(
2 input A,

3 input B,

4 input C,

5 output X

6 );


8 // Circuit Description


10 endmodule

As we need to tell the tools about the delay of each of the gates, we will need to define the name of each internal wire.

1 wire N1, N2, N3;

Now we describe each gate in the circuit one by one.

1 // AND gate with 1ns delay
2 assign #1 N1 = A & B;

3 // Not Gate with 1ns delay

4 assign #1 N2 = ~B;

5 // And Gate with 1ns delay

6 assign #1 N3 = N2 & C;

7 // Or Gate with 1ns delay

8 assign #1 X = N1 | N3;

So the Verilog file that describes the circuit, with delay information and time scale for each delay of each gate, looks as follows:

1 `timescale 1ns / 1ps
2 module CombCirc(

3 input A,

4 input B,

5 input C,

6 output X

7 );


9 wire N1, N2, N3;


11 // AND gate with 1ns delay

12 assign #1 N1 = A & B;

13 // Not Gate with 1ns delay

14 assign #1 N2 = ~B;

15 // And Gate with 1ns delay

16 assign #1 N3 = N2 & C;

17 // Or Gate with 1ns delay

18 assign #1 X = N1 | N3;


20 endmodule

Step 2: Create the Test Bench and Simulate the Circuit

As the purpose of this test bench is to demonstrate the glitch, instead of simulating all of the possible input transitions, we will craft an input sequence that can trigger the glitch in the output of the circuit. By observing the circuit, there is an unbalanced path between input B and output X (i.e., there are two paths to propagate the changes of B to the output with different delays). So the glitch will happen when A and C are constant and B toggles. Here is the description we are going to create in the initial block of Verilog test bench:

1 integer k = 0;

3 initial begin

4 // Initialize Inputs

5 A = 0;

6 B = 0;

7 C = 0;


9 // Wait 100 ns for global reset to finish

10 // Add stimulus here


12 for(k = 0; k < 4; k=k+1)

13 begin

14 {A,C} = k;

15 #5 B = 1;

16 #5 B = 0;

17 #5 ;

18 end

19 end

Simulate the test bench in the Vivado Simulator, and you will get the waveform display, as shown in Fig. 2 above. The red circle on the waveform specifies the glitch. So the glitch actually happens when A is 1, C is 1 and B toggles from 1 to 0. The duration of the glitch is 1ns.

Step 3: Test Your Knowledge

Now that you've completed this project, try these modifications:

1. Assume the OR gate in the previous circuit has a propagation delay of 2 ns. Simulate the circuit again and try to find the glitch. If there is a glitch, when does it occur and what is the duration of the glitch? If there is no glitch, can you explain why? Think about the differences in path delay for signal B.

2. Assume the delay of all gates are 5 ns. Modify the CombCirc module and the test bench properly and try to find the glitch. If there is a glitch, when does it occur and what is the duration of the glitch? If there is no glitch, can you explain why?

<p>Nice project.</p><p>And to make it clear: Such problems are not only theoretical. I made once a fully customizable code-lock in solid state (Only gates of the 74 and 4000-series). In one point i had to insert 2 NOT-gates to delay the signal enough to allow the corresponding signal on another way arrive BEFORE the (now artificially delayed) signal reached a common gate.</p><p>If somebody has interest, i am sure i can rally up the schematics from my archives... in the end it was made under Creative Commons <br>Attribution-NonCommercial-ShareAlike 2.5 Switzerland License. :)</p>

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