This is an introduction to setting up a microblaze processor for the Nexys4 Artix-7, using Vivado 2014.1 .

Step 1: Create a New Project in Vivado

1. Create a new project. (Image 1)

2. Press Next

Step 2: Name the Project

3. Press Next, name the project Hello_World, and select create project subdirectory (Image 2)

Step 3: Select RTL

4. Press Next, select RTL Project (Image 3)

5. Press Next

6.Press Next

7. Press Next

Step 4: Select the FPGA

8. At the Default Part screen, select the parts, corresponding to the image (Image 4).Press Next.

9. Press Finish

Step 5: Create the Processor

10. In The Flow Navigator, under IP Integrator, click "Create Block Design" (Image 5)

Step 6: Name Your Block Design

11. Change Design name to be system (Image 6)

Step 7: Add IP

12. Click on "Add IP" in the green bar at the top (Image 7)

Step 8: Select Microblaze IP

13. Begin to type "Microblaze" and select the processor (Image 8).

A block representing the processor is added to the block design.

Step 9: Run Block Automation

14. Click on "Run Block Automation" and choose the /microblaze_0 dropdown (Image 9)

Step 10: Select Debug & UART

15. Change the "Local Memory" to 32Kb and the "Debug Module" to "Debug & UART" (Image 10) and click OK. It generates several additional blocks and places them on the board.

Step 11: Connect the Processor

16. Double click on the block labeled "clocking wizard" (Image 11)

Step 12: Change Clock Source

17. Change the clock source to "single ended clock capable pin" (Image 12)

18. Click on "Run Block automation" and choose /clk_wiz_1/clk_in1 Press ok

19. Click on "Run Block Automatic" and choose /reset_rtl_0 and select "Active Low" Press OK

20. Click on "Run Block Automation" and choose /clk_wiz_1/reset and select "Active high" Press OK

**Note** Your design might have generated with different names i.e. reset_rtl_0 might be reset_rtl

Step 13: Add Constraints

21. Expand the "Constraints" folder, under the "sources" tab. Right click and select "Add Sources" (Image 13)

22. Select "Add or Create Constraints" and press next.

23. Press "Add Files" and navigate to where the file "Nexys4_Master.xdc" is saved. If you need this file, download it from http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4

24. Press OK and finish, make sure the box to copy the file to your local project is selected.

25. Open the constraints file, and uncomment lines: 8,9,10, 59,60, 194 and 195

26. Modify the port names in those properties, to match the port names in your Block Diagram

set_property PACKAGE_PIN E3 [get_ports clock_rtl] 
set_property IOSTANDARD LVCMOS33 [get_ports clock_rtl] 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clock_rtl] 
set_property PACKAGE_PIN P4 [get_ports reset_rtl_0 ] 
set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0 ] 
set_property PACKAGE_PIN E16 [get_ports reset_rtl]  
set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl] 

27. Make sure to save the updated .xdc file (Press Ctrl-S)

Step 14: Create HDL Wrappers

28. Right click on "system.bd" in the sources window. Select "Create HDL Wrapper"

29. Expand the system_wrapper and Right click on "system.bd" in the sources window. Select "Generate output products"

30. Click "Generate Bitstream" and wait for the synthesis and implementation to complete.

31. Click on "Open implemented design" and press ok. (Image 14)

Step 15: Export to SDK

32. Once the design opens. Select File > Export > Export Hardware for SDK

33. Check the box "Launch SDK", and "Export Hardware" and "Include Bitstream"

34. Once the SDK is open. Select File > New > Application Project

35. Name your project hello, press ok (Image 15)

Step 16: Select Demo "Hello World" Project

36. Select the test project "Hello World" (Image 16) and press ok

Step 17: Program FPGA

37. Turn on the FPGA and select: Xilinx tools > Program FPGA

38. Leave the settings alone and press "Program"

39. Select your project folder called "hello". Open the src folder and open helloworld.c

40. Select Run > Debug Configurations. Under STDIO Tab, check connect STDIO to Console, and choose JTAG UART from the dropdown list. (Image 17)

Step 18: Run "Hello World" on Microblaze

41. Flip Switch 15 on the Nexys4 board (This turns off reset, if you press Run, and there is an error, try flipping the switch the other direction). (Image 18)

42. Right click on "hello" folder, select: Run As > Launch on Hardware (GDB) The console should say "Hello World"

<p>I recently came across your project and managed to run it on my Basys3. Thank you very much.</p>
<p>Glad to hear. :) The Basys and Nexys share the same family of FPGA.</p>
Hi, i am very new.we have vc707 board. Can i implement same in vc707 board? Are any specific changes required? And i want to display Hello world in Lcd ? Is it possible?
<p>I love your project! We have the Nexys4 DDR coming out. Would you be interested in re-doing this project using that board? I'll send you one for free!</p><p>http://digilentinc.com/Products/Detail.cfm?NavPath=2,1301,1319&amp;Prod=NEXYS4DDR</p>
<p>Hi,</p><p>Why the system have two reset one active high and the other active low. It's possible to reudce to just one? (active high or low)</p>
<p>Yes, If you double click on the clock generator, you can select the outputs tab, and remove the separate clock reset. Make everything active low, and use btnCpuReset in the constraints file.</p>
Hi Skyberrys, thanks for fast and useful answer.<br>Another one if possible.<br>I made some modification:<br>- one clock active low, no clock wizard reset<br>- micro blaze just debug no debug+uard<br>- added Uartlite set for 115200bps, with xdc modification for rx, tx<br>- connect Nexys4 with pc with terminal prog (putty)<br><br>So building the classic Hello World in SDK I have some strange behavior:<br>- at the firs run i get &quot;ello World!&quot; (I lose first letter)<br>- pressing reset one time I get the correct &quot;Hello World!&quot;<br>- pressing reset again I get nothing ....<br><br>Why this happen? Any ideas?<br>Second reset clear prog memory ? And if yes whit first reset No?<br><br>Thanks <br><br><br>
Hi Skyberry thankyou for fast and useful answer.
<p>HI,</p><p>Why the system have two reset one active high and the other active low. It's possible to reudce to just one? (active high or low)</p>
<p>I have a question if anyone can help me. I was wondering how would you assign a different segment to different anodes example if I want an0 to display 3 and an4 to display 1 at the same time how would I do that? right now I could only display the same number for any of the anodes that that are on example would be if I have an1 and an5 on and have the segment code to display a 7 it will therefore display 7 at the same time on both of those anodes. Any help would do thanks.</p>
<p>Hello,</p><p>You want to switch back and forth between an0 and an4, with a frequency of at least 60Hz. This means that some of the time an0 will be low, and the cathodes will be configured for 3 and other times an4 will be low with the cathodes configured for 4. </p>
Thank you skyberrys! that seemed to work.
<p>Anything that softens the learning curve with FPGAs is a win in my book. Thanks for sharing!</p>

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Bio: Computer engineering grad student. I make the path.
More by skyberrys:Setting up Microblaze on the Nexys4 FPGA Board Hemisphere Keyboard 
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