Introduction: Getting Started With Xilinx Vivado W/ Digilent Nexys 4 FPGA 1 - Build Multiple Inputs AND Logic Gate

I do this instructable because it looks like there is not simple getting started tutorial to teach people to use the latest Xilinx Vivado CAD tool. So, I want to use the simple multiple inputs gate design to walk through Xilinx Vivado CAD. I will use Verilog Hardware Design Language to create the logic design. The design will be then implemented in the Digilent Nexys 4 FPGA (Field Programmable Gate Array) development board.

Digital / Logic design is a fundamental but important knowledge. It is the design of circuits and systems that form the base of all electronics. FPGAs are programmable semiconductor devices that are based around a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. If you want to know more about FPGA, you can go to Xilinx or National Instruments website.

Verilog is basedon the C programming language and is the most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. You can find out the details in the Digilent Intro to Verilog Project

Step 1: Go to Xilinx Website

Go to Xilinx website http://www.xilinx.com/products/design-tools/vivado/ and then click downloads in the left hand side of the webpage.

Step 2: Download the Installation Executable File

Select the operation system you are using and click the link

Step 3: Login the Xilinx Website / Register As Xilinx Customers

Login the Xilinx website (or register as Xilinx user if you don't have an account). Once you log in, you will be direct to the download center. Verify the personal information and then click next until you start to download the installation file.

Step 4: Run the Executable File

It takes few minutes to download the executive file. Once it is done, click run. Then, the installer will pop up. Click Next and then log in again. Then, it will starts to download. This process will take a few hours.

Step 5: Create Free Vivado Webpack License

Once you finish the download, you can create the free Vivado Webpack license. You can find out the instruction at http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/iil.pdf (page 6-9)

Step 6: Open the Vivado

Once you have finished the download and created the free license. Open the Vivado Webpack (If you are window users, you will find the program in the All Programs or desktop.

Step 7: Create a New Verilog Project

Click Open New Project. A new project creation wizard will pop up. Click Next and then name the project "project_1_multiple_inputs". Select the folder path and create project sub-folder. Choose RTL project

Step 8: Create Source File for the Project

Click "Create File". Then, there is "Create Source File" pop up. Choose Verilog in file type. Name the file "Circuit1" and choose file location to <location to project>. Click OK --> Next --> Next. Then, you need to choose the part. Digilent Nexys 4 is based on XC7A100T-1CSG324C. So, we should choose family: Artix 7 and package:CG324, speed grade: -3. Highlight the XC7A100T1CSG324-3 (last option) and click Next --> Finish.

Step 9: Create Inputs & Outputs

Name the input as x and output z in the port name field. Choose input or output under direction field. Click OK

Step 10: Write the Verilog Module

First, hide the "Design Run" Panel by clicking the minimizing button

Double click "Circuit1" module to start to write the Verilog program. You will see there are some default syntax.

module Circuit1(

input x,

output z

);

endmodule

Module Circuit1 --> Circuit 1

input x --> the input we created

output --> the output we created

The parenthesis ( ) in the module definition

The semi-colon ";" to run the syntax

We want 4 inputs, so we do an array of 0 to 3. The syntax will be

module Circuit1(

input [3:0] x, // create 4 inputs

output z // create one input

);

endmodule

Then, we also want to assign the AND relationship to the output. So, we write

assign z = &x;

Step 11: Instantiate the Verilog Module

We want to instantiate the module so that the design can be implemented in the FPGA board.

Highlight the Circuit1 module. Click Add Sources

Select Add / Create a Design Source and Click Next

Click "Create File" and then name the file "circuit1_top". Choose the Verilog and . Click OK --> Finish

We want to use switch as inputs and LED as output in the Nexys 4, so we create sw (switches), led (LED) as inputs and output in the circuit1_top module. Click OK.

Double click the circuit1_top module.

Write the following Verilog program

module circuit1_top(

input [3:0} sw, // create 4 inputs

output [0:0]led // create one output

);

circuit1 C1 (.x(sw),.z(led[0])); //instantiate the x and z to switches and LED

endmodule

Step 12: Set the Circuit1_top As the Top Module

Right click the circuit1_top and set it as the top module under hierarchy in the project manager panel

Step 13: Add Constraint File

Go to Digilent Nexys 4 webpage and download the xdc zip file

http://www.digilentinc.com/Data/Products/NEXYS4/Ne...

Save under a directory that you can have access to and unzip it

Under the project manager panel. Double click "Add Source". Choose "Add or Create Constraint".Click Next

Click Add file. Choose the "Nexys4_Master.xdc" . Click Finish

Expand the Constraint folder under sources panel and double click the xdc file

Uncomment the SW 0 to 3 by deleting the "#". The bold parts should not have any "#" at the beginning

Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
set_property PACKAGE_PIN U9 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] Bank = 34, Pin name = IO_25_34, Sch name = SW1 set_property PACKAGE_PIN U8 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 set_property PACKAGE_PIN R7 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]

Uncomment the led 0 by deleting the "#". The bold part should not have any "#" at the beginning

Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
set_property PACKAGE_PIN T8 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]

Step 14: Run the Synthesis and Implementation

Double click "Run Synthesis" under the project manager panel . Vivado will ask you to save all changes you made before the synthesis. Click OK to save all changes to start the synthesis. Once it is successfully completed, the implementation pop up. Choose implementation and Click OK.

Double click generate bitstream file and generate the bitstream file

Step 15: Target the Hardware

Expand the Hardware Manager and then double click the target hardware. A wizard pops up. Click Next

Choose connect to local server (machine)

Grab the Digilent Nexys 4 and connect it to the USB port of the computer. Turn on the Nexys 4. There is a test demo showing up (LED is blinking and Seven Segment Display is showing 1 to 5). Click Next.

Vivado will detect the Nexys 4 automatically. Click Next --> Next to open the hardware

Step 16: Program the Device

Double click Program Device.

Step 17: Result

So only SW0, SW1, SW2 and SW3 all switch on, then LD0 will be on.

The upper picture shows all switches are off, so LED is off. The bottom one shows all are on, so the LED (LD0) is on

The project file has been attached.

Comments

author
nicolas.edwards.5 made it!(author)2014-10-05

Where are the actual pin assignments done. I see where you create the inputs and outputs for your module. I see where you use the constaints file to set the switches and leds you are going to use. Where are you doing the actual assignments of input/output of the module to input/output of the fpga.

author
alexwonglik made it!(author)2015-07-20

Hi Nicolas, sorry for the late reply. I used the master xdc file provided on the Nexys 4 webpage. You can also do own IO planning in the implementation but it takes more times.

author
Lexl made it!(author)2014-08-06

I have a question if anyone can help me. I was wondering how would you assign a different segment to different anodes example if I want an0 to display 3 and an4 to display 1 at the same time how would I do that? right now I could only display the same number for any of the anodes that that are on example would be if I have an1 and an5 on and have the segment code to display a 7 it will therefore display 7 at the same time on both of those anodes. Any help would do thanks.

author
alexwonglik1 made it!(author)2014-08-22

Hi Lexl, are you referring to the hardware design? If so, are you using Nexys 4?

author
mjafarin made it!(author)2014-07-18

This was great help for me as I have just started learning Verilog and using this board for it. Of all the resources I have been using to move forward yours was the most useful.

author
craftclarity made it!(author)2014-06-12

Thanks for posting this, I'm sure it will prove useful for users of Xilinx...!

author
alexwonglik made it!(author)2014-06-13

Yes. I am still learning each feature the Vivado but I start to like it already. And, yes Xilinx FPGA is useful.

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