In this project we have three working area. In the first step, the analyse of the polar codes by using List Decoding Algoritm methods will be assimilated by using matlab simulation. In the second step the settlement processing of polar codes by using List Decoding Algoritm will be implement on FPGA digital equipments. Therefore, by using VHDL hardware language, we will do hardware design. In the third step of our studying, to increase the performance of the implemented polar codes by using List Decoding Algoritm, our suggested methods will be experienced. By experiencing the suggested methods on FPGA atmosphere, the performance gainings considering classical methods will be calculated in BER.

## Step 1: Polar Encoder

Let’s show length data sequence as. The polar code of this data vector is calculated from the first formula in figure. Here, x_1^N , is code vector and it contains N number of bite. G_N is a generator matrix and calculated by using the second formula in figure. F is kronocker force of matrix. B^N matrix is calculated by using last formula in figure. R^N is permutation operator. The polar code can be expressed in pictorial. The polar code of 4 units lenght bit data vector is shown in the graphic below in picture.

## Step 2: Polar Decoder

When polar coding is applied, the formulas given in the picture are applied on the tree that you see in the picture. The first bit is found by going up step by step. The steps are determined according to the application of the formulas L1 and L2 and all the data are found.

Block Diagram