The main topic process video using a FPGA with VHDL as a hardware description language. The target board is in this case ZYBO board from Digilent based on the Xilinx SoC Zynq family z7010.
The main function is to create a small functional project, documented and with some application examples, where other users or students can add easily their own VHDL code using Vivado HLS.
The Zybo board have one HDMI and one VGA ports.
Each of these video connectors could be used as a sink or as a source. In this project, the HDMI will be used as a input because almost all the normal photo cameras or action cameras they have an HDMI output, that can be used conveniently for this purpose. Another Digilent Zynq-based development boards they have different sink/source video connectors.
HDMI --> Video input
VGA --> Video output
In this project only the FPGA part of the Zynq SoC. The processor system (PS) of the Zynq chip could also be used to process this video by software. In the next table the pros and cons are resumed:
FPGA processing with VHDL
- High speed and parallel computing àHigh frame rate and resolution possible
Low abstraction level video processing
Software processing with ARM processor
- Low, mid or high abstraction level video processing
- Processing speed limited by the processor and possible bottle neck on the processor à low frame rate and resolution
Note: This project is still under construction and is going to be edited and improved soon.
Step 1: Create a New Vivado Project
After opening Vivado, first you need to create a new project on your workspace you want to work in.
Later name your project and choose the project location.
Choose Zybo as a target board or another Zynq board you want to use.
Step 2: Create a Block Diagram With Basic
Add a new Zynq_Processing_system diagram. Clicking on the block properties you can delete the AXI GPO interface and set the clock output of the PS to 200 MHz.
Also add the IPs from Digilent Dvi2rgb and rgb2vga and connect them like the last picture
Resuming: The block diagram shown in the Picture was made to interconnect different modules. The following main IPs were inserted
- Dvi2rgb: It converts the HDMI input into RGB raw video. From Digilent library.
- Rgb2vga: it converts the raw video into VGA output. From Digilent library.
- Processing_system7: This is an special block, that contains the configuration of the processing system of the Zynq. In this case only the clock output signal will be used from the processing unit.
- VideoProcessing: A self-made VHDL block. Here the user-application code should be inserted and modified. (Explaination on the next step)
Additional to these blocks two constants are used to configure the HDMI port as a sink.
Step 3: Insert a VHDL Resource
Now the user application block should be created, or imported. Therefore press ctrl+A or right click on the sources and select “add sources”.add a new source file.
Create a new file with VHDL with some name, for example VideoProcessing.
Here Vivado ask you to insert the input and output of your block. This can be defined later, but it is good to create at least one input in order to Vivado recognize it as a block and let you instanciate without modifying. The inputs and outputs can be always modified later on the VHDL file.
After that the new module can be on the block diagram instanciated. Right click on the empty diagram and select “add Module…”
One the module is instanciated, pressing the key F7 you can edit the VDHL code.
Step 4: Add Additional Onboard Perifericals Like Leds, Buttons or Sliders (optional)
To include some complementary options the sliders, buttons and leds are routed to the application block. The new block diagram should look like the picture.
Step 5: Now You Can Insert Your VHDL Code on the Application Block
Once added the VideoProcessing module, pressing F7 (or searching it on the sources) you can edit the code. An example of a minimal code can be found on the attached module.
Step 6: Create a Wrap
Create a new wrap before synthetise the block diagram.
Step 7: Synthesis, Implementation and Bitstream Generation
Add the constraints file attached.
Now you can run the synthesis and when it finalices without errors, you can open the synthetized design and check if all the pins are connected right, specially if you named the output pins differently.
Then run the implementation and after that generate the bitstream.
Step 8: Export Hardware and Launch SDK
Export the Hardware as shown in the pictures and launch SDK.
Step 9: Create a New Board Support Package and a New Application
Now create a board support package as the pictures show.
After that make a new application as a hello word template.
Program the FPGA and run (or debug) the hello word example
Step 10: Program FPGA and Run the Hello World Code
In this small example, the color channels are exchanged. Now the blue input is green and so on.