Step 1: Circuit Analysis
The shield replies on a MAX481CSA chip to convert TTL level to 485 level. As shown in the schematic, the enable signals for the receiver and transmitter are tired together, and controlled by the drain of MOS transistor Q1. The drain of Q1 is in turn controlled by the data signal (TX). When the data transmitted is “1”, the RE/DE signal will be “0”, and the chip is in the receiving state, and the chip will not drive the A,B differential data lines. If there is no external pull-down circuit, the data displayed on data line will be uncertain. This is also a cause of the error. But it is not the root cause of the issue when communicating at high speed. In next section, we will analyze the timing sequence, and we can clearly see the issue.
Step 2: Timing Analysis
Let closely look at the timing diagram of DE/RE signals.
When the communicate speed is slow, the period of timing signal is big. RX DATA DELAY is relatively smaller compared to the clock period, and the sample time can cover the period time. However, when the communicate speed is high, the timing signal period becomes smaller. The sample time is shorter, and the RX DATA DELAY can’t be covered by the sample time, which will lead to sample data error.