The combinational logic circuit (CLC) is an important chapter in the project
activity of the electronic equipments. If the number of variables is greater than three the project
activity with Veitch-Karnaugh diagrams become very difficult. On the other side, the feed-
forward artificial neural networks have several characteristics like noise immunity, fault
tolerance etc. that can be advantages for logical circuits made by these networks. In this papers
we presents a new method in simulation of the combinational logic circuit with the neuronal
network. There are two important advantages that we can remark: the number of transistors is
reduced and the design will become simpler.


The traditional calculator doesn’t always manage to face the problems that
require intensive calculus such as pattern recognition, robots` movement control,
decisions` taking based on a large quantity of data with noise etc. As a result, other
methods of information processing were approached and distributed processing is one
of them. One of these non-conventional direction of information processing, that
meets many of the above requirements is represented by artificial neural networks
(neural calculus).

The present paper approaches the simulation, with the help of neural
networks, of combinational logical circuits (CLC). Section 2 presents notions about
CLC design and illustrates the difficulty of designing complex CLC. Section 3 shows
an example of simulation with feed-forward artificial neural networks. In the last
section some conclusions on our approach are shown.

A combinational logic circuit (CLC) is an electronic circuit with n inputs,
noted by X1, X2, …, Xn, and m outputs, noted by Z1, Z2, …, Zm, for which the outputs
could be expressed according to inputs using a mathematical model such as:

Z1 = f1(X1, X2, …, Xn)

Z2 = f2(X1, X2, …, Xn)


ZI = fi(X1, X2, …, Xn)


Zm = fm(X1, X2, …, Xn)

In the synthesis of a circuit CLC generally one starts by classifying the functioning
conditions according to the requirements imposed by a table of truth and the
specification of the operation and non-operation state. The following steps are

Problem utterance; Formulation of the truth table;

Minimization of the truth function;

Correlated minimization of the commutation functions; Scheme analysis and
hazard elimination;

Hardware implementation of the logical functions.

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