Introduction: Combinatorial Logic Simulator

The combinational logic circuit (CLC) is an important chapter in the project
activity of the electronic equipments. If the number of variables is greater than three the project
activity with Veitch-Karnaugh diagrams become very difficult. On the other side, the feed-
forward artificial neural networks have several characteristics like noise immunity, fault
tolerance etc. that can be advantages for logical circuits made by these networks. In this papers
we presents a new method in simulation of the combinational logic circuit with the neuronal
network. There are two important advantages that we can remark: the number of transistors is
reduced and the design will become simpler.


The traditional calculator doesn’t always manage to face the problems that
require intensive calculus such as pattern recognition, robots` movement control,
decisions` taking based on a large quantity of data with noise etc. As a result, other
methods of information processing were approached and distributed processing is one
of them. One of these non-conventional direction of information processing, that
meets many of the above requirements is represented by artificial neural networks
(neural calculus).

The present paper approaches the simulation, with the help of neural
networks, of combinational logical circuits (CLC). Section 2 presents notions about
CLC design and illustrates the difficulty of designing complex CLC. Section 3 shows
an example of simulation with feed-forward artificial neural networks. In the last
section some conclusions on our approach are shown.

A combinational logic circuit (CLC) is an electronic circuit with n inputs,
noted by X1, X2, …, Xn, and m outputs, noted by Z1, Z2, …, Zm, for which the outputs
could be expressed according to inputs using a mathematical model such as:

Z1 = f1(X1, X2, …, Xn)

Z2 = f2(X1, X2, …, Xn)


ZI = fi(X1, X2, …, Xn)


Zm = fm(X1, X2, …, Xn)

In the synthesis of a circuit CLC generally one starts by classifying the functioning
conditions according to the requirements imposed by a table of truth and the
specification of the operation and non-operation state. The following steps are

Problem utterance; Formulation of the truth table;

Minimization of the truth function;

Correlated minimization of the commutation functions; Scheme analysis and
hazard elimination;

Hardware implementation of the logical functions.

Step 2:

A delicate problem in the case of the classical approach of CLC circuits` synthesis
is that not always an absolute optimum rigorous scheme is achieved. Thus, in the case
of synthesis of the complex functions with a high number of input variables (those
with n>6), with many outputs and undetermined states, the algebraic and topological
methods are very difficult to be applied.
In the following we illustrate the problem of designing CLC by an example. In
figure 2 we show the process of minimisation with Veitch-Karnaugh diagram, and in
figure 3 is shown the resulting CLC.


This paper proposes a special treatment of these CLC’s by means of the utilization
of neural networks. The solution was suggested by the functional similitude existing
between a CLC and a neural network with n inputs and m outputs. In fact, a neural
network of three layers was used, the first layer having n (4) input neurons and the
third m (2) output neurons (fig. 4). For the neural network the set of input and output
data is given by the truth table in figure 2.

Step 4:

The simulations have shown that, for a network in configuration 4:6:2, the I/O
dependence of the CLC can be already achieved. If we note that for this network are
necessary 12 neurons (including the passive input neurons), it results an equivalent of
12 gates, in opposition with the CLC in figure 3 which uses 18 gates of several kinds.
It is obvious that, in hardware implementation, a neural approach for realizing CLC’s
functions can be competitive. In figure 5 one can see the real output of the “neural”
CLC and the desired output, for every combination of inputs in truth table


As a conclusion, the methodology of combinational circuits simulation, with
the help of neural networks, requires the following steps:
Step 1. Formulation of the truth table for the chosen combinational circuit;
Step 2. Selection of a neural network with three layers which has n neurons on the
first layer, a number of neurons in the hidden layer that will be find and m neurons in
the output layer;
Step 3. Training the neural network using the truth table;
Step 4. Verification of the correct functioning of the network;
Step 5. Network hardware implementation.

Step 6: Software Design

Step 7:

Step 8: 3D Design

Step 9:

Step 10:

Step 11:

Step 12:

Step 13: Finally


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