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Hi I was interested in trying this project. When I attempt to synthesize the project I receive an error. Any ideas on how to get around this? [Synth 8-549] port width mismatch for port 'addra': port width = 18, actual width = 19 ["C:/Users/Khugh/OneDrive/Documents/embedded_systems/final/fivenine/ov7670_top.vhd":144]