Datasheet
-Materials:
-Leds
-Wires
For 1 Led, verilog code is:
module ledblink(clk,led);
input clk; output led; reg led;
reg[23:0] cnt;
always @(posedge clk) begin cnt<= cnt + 1'b1; led<=cnt[23];
end
endmodule
if you need more information about this tutorial, check my Blog
Comments
CameronC32 8 years ago
That is one compact FPGA!
I use altera too. I have the max 10, and the cyclone 2.