Designing a 4-Bit Adder in Quartus II
Intro: Designing a 4-Bit Adder in Quartus II
The purpose of these instructions is to create a 4-bit adder in Quartus II. A 4-bit Adder is a simple model of a calculator. It takes in two numbers of 4 bits each, allowing us to take numbers 0-15, but we will be using numbers 0-9. The numbers are then added together. The circuit is made in Quartus II and then is programmed onto a Field Programmable Gate Array (FPGA) which allows the circuit to be used.
This project is intended to be for fun or could be a final project for a class, but is mostly to become more familiar with logic circuits. This project will make more sense if you have already taken or are currently taking a digital logic class and have a basic understanding of logic gates. Some basic commands of Quartus are also covered if you have never used it.
The FPGA has buttons, switches, LEDs, and number displays to accommodate most circuits. Quartus 2 can be purchased for around $3,000-$4,000; although, the web edition of the software is free, but still requires the purchase of an FPGA. I found FPGAs online for around $200. I used the campus software, so I did not have to purchase any equipment. It took me 6 hours to complete the adder from scratch my first time. My hopes with these instructions are for you to be able to complete the 4-bit adder in less than 5 hours. Completion of this circuit will bring you greater understanding and fulfillment with its complexity.
Note: Pictures at the beginning of each page show given steps in the process. They are to prevent confusion
STEP 1: Starting Quartus
1) If not already installed, install Quartus onto your computer.
Note: I did not have to install Quartus since I used a campus computer. Follow the installation wizard and everything should work fine.
2) Open Quartus from your main window.
3) The project wizard should appear. Click on create a new project.
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4) The first page tells you about the project wizard. Click next to go to the next page.
5) Select a directory to work from.
Note: Any directory is fine. It is simply where you will save your files. It is best to create a folder specifically for any project you do.
6) Name the project 4BitAdder. This will also appear as the top level design entity.
7) Click to the next page.
8) We will be starting from scratch, other than the basics that are included in the program, so click next again.
9) Choose the family name of the FPGA you have. (Cyclone, stratix, etc.)
10) Your device will have a specific name given in the scroll bar. Select it and hit finish. The last two pages will not be changed.
a) To figure out the family name and specific name of your device, find the processor on the FPGA. It is a larger chip with ALTERA written on it.
b) The family name will be on the second line in slightly smaller print than ALTERA.
c) Below the family name is the device’s specific name, containing letters and numbers.
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11) The project will load with a blank screen saying Altera Quartus II. In the upper left corner, click on file, and then click on new from the drop down menu that appears.
12) Select Block Diagram/Schematic File (BDF) from the window that appears. The screen will be white with small dots.
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13) Save the file right away under the name 4BitAdder. The file should default to this name when the save screen appears.
Note: To save, click file, then save as. You can also click on the floppy disk in the tool bar to save after parts are added.
Caution: Save often. Computers and software are known to crash. To keep from losing information and redoing steps, save your files whenever you think of it.
This file will be where the main project comes together. Smaller components will be created in other files and made into a block, where only the inputs and outputs are seen without all of the gates and mess. These blocks are smaller and create less clutter for the project.
Note: I did not have to install Quartus since I used a campus computer. Follow the installation wizard and everything should work fine.
2) Open Quartus from your main window.
3) The project wizard should appear. Click on create a new project.
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4) The first page tells you about the project wizard. Click next to go to the next page.
5) Select a directory to work from.
Note: Any directory is fine. It is simply where you will save your files. It is best to create a folder specifically for any project you do.
6) Name the project 4BitAdder. This will also appear as the top level design entity.
7) Click to the next page.
8) We will be starting from scratch, other than the basics that are included in the program, so click next again.
9) Choose the family name of the FPGA you have. (Cyclone, stratix, etc.)
10) Your device will have a specific name given in the scroll bar. Select it and hit finish. The last two pages will not be changed.
a) To figure out the family name and specific name of your device, find the processor on the FPGA. It is a larger chip with ALTERA written on it.
b) The family name will be on the second line in slightly smaller print than ALTERA.
c) Below the family name is the device’s specific name, containing letters and numbers.
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11) The project will load with a blank screen saying Altera Quartus II. In the upper left corner, click on file, and then click on new from the drop down menu that appears.
12) Select Block Diagram/Schematic File (BDF) from the window that appears. The screen will be white with small dots.
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13) Save the file right away under the name 4BitAdder. The file should default to this name when the save screen appears.
Note: To save, click file, then save as. You can also click on the floppy disk in the tool bar to save after parts are added.
Caution: Save often. Computers and software are known to crash. To keep from losing information and redoing steps, save your files whenever you think of it.
This file will be where the main project comes together. Smaller components will be created in other files and made into a block, where only the inputs and outputs are seen without all of the gates and mess. These blocks are smaller and create less clutter for the project.
STEP 2: Clock Generator
The clock drives the overall circuit. Originally, the clock is generated at 10MHz, much too fast for our uses. The clock will be scaled down using T flip flops. Your clock may be at a different frequency. Check to see what frequency it is and adjust the number of T flip flops. Our circuit = (10^7)/(2^28). Getting the clock to the right frequency makes sure the process of adding doesn't occur too quickly and out of your control.
1) Begin a file named clock_divider_1024.
a) File->new
b) Select BDF
c) Save under given name
2) Place 10 T flip flops within the space.
a) 1) To add components, click on the symbol tool in the tool bar. (It looks like a D with two wires on the left and one on the right.)
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a) 2) You can also double click in the white space to bring up the symbols window.
b) The symbols window loads with two libraries. One has all the files in the project that are made into the simpler blocks. The other is the default library that comes with Quartus. Click on the + beside the default library to expand.
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c) Our components are under the primitive folder. Click on the + to expand it.
d) The flip flops are under the storage file. Click the + to expand it.
e) Select tff.
f) Since we want multiples, click on the option “repeat-insert mode”.
g) Press OK and click in the white space to add T flip flops. (one per click)
Note: To stop any command or leave a new window, press the escape key.
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3) Arrange the flip flops into two horizontal rows of 5 each. Leave about 2 blocks of space between flip flops.
Note: 1 block will be the same area as the flip flop for these instructions.
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4) Add 8 2-input AND gates.
a) Open the symbols window like you did for the T flip flop.
b) The folders should still be expanded. Expand the logic folder by clicking on the +.
c) Select AND2. We want multiples, so make sure to click the option “repeat-insert mode”.
d) Click to add AND gates.
5) Place the AND gates between each flip flop, starting after the second flip flop.
Note: It is best to go from left to right for circuit flow.
a) If you have already added the AND gates and need to arrange them, simply click and drag. Release the left mouse button where you want the gate.
6) Add an input pin before the first flip flop.
a) The pins are under the PIN folder. Expand it to select the input tab.
7) Label the input pin CLK_IN by double clicking on pin_name and changing it.
8) Click on the orthogonal node tool.
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9) Connect the input pin to each of the triangles, also called clock input, on the T flip flops.
a) Click and drag to create wires. Make sure the wires connect to the wire on each component.
Caution: A “node” forms when three or more wires intersect at a right angle. This node is looks like a dot. Be aware of which wires are being connected to each other. It can mess up circuit flow.
10) Add VCC from the parts list.
a) VCC is located under the “other” folder.
11) Using the orthogonal node tool, connect VCC to T of the first flip flop and PRN and CLRN of every flip flop.
12) Connect Q of the first flip flop to T of the second flip flop.
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13) Connect one input of each AND gate to the Q of the flip flop right before it.
14) Connect the other input of the AND gate to the T of the flip flop right before it.
15) Connect the output of the AND gate to the T of the flip flop right after it.
16) Add an output pin.
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17) Label the output pin CLK_OUT.
18) Connect the Q of the last flip flop to the output pin.
The T flip flop works as a clock divider. With T of the first flip flop connect to VCC (high voltage), the first flip flop toggles its output (from 1 to 0 or vice verca) Q at each clock cycle. Q is connected to T of the second flip flop, so Q of the second flip flop will only toggle its value when its T is 1 and the clock goes from 0 to 1. From there, every other flip flop requires that every flip flop before it have value 1 before it is allowed to change from 0 to 1. The period of each clock cycle becomes longer, slowing down our clock.
19) Save the file.
20) To make the file useable as a block, click on Processing, then Analyze current file.
21) After the file has been analyzed, click on file, go down to create/update, and from the menu that appears beside it click on Create Symbol Files for Current File.
Our circuit has now been made into a block with internal parts hidden and only the inputs and outputs showing up. The original circuit will not be changed, only when it is used in other files. To use in another project, the .bdf and .bsf files for each circuit file must be copied to that project’s folder.
22) Open a new file (bdf) and call it clock_generator.
23) Add 2 of the clock_divider_1024 parts just created.
a) From the components window, expand the 4BitAdder folder.
b) Select clock_divider_1024 and add it to the file.
24) From the clock_divider_1024 file, copy the entire circuit and paste into the new file.
25) Cut the number of flip flops down to 8 and AND gates down to 6.
This can be done be done by
a) Delete everything after the 8th flip flop, except the output pin.
b) Connect Q of the 8th flip flop to the output pin.
c) Delete the wire that connected T of the 8th flip flop to the AND gate that used to be after it.
26) Delete the wire connecting CLK_IN to the first flip flop.
27) Connect CLK_IN to the input (left side) of one Clock_divider_1024.
28) Connect the output (right side) of the same clock_divider_1024 to the input of the second clock_divider_1024.
29) Connect the output of the second clock_divider_1024 to the clock input (triangle) of the first flip flop.
30) Make sure VCC is connected to PRN and CLRN of every flip flop, as well as the T input of the first flip flop of the circuit.
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31) Save the file.
32) Analyze the file. (processing->analyze file)
33) Create a symbol for the file. (file->create/update->create symbol)
34) In the file 4BitAdder, add the clock_generator.
STEP 3: State Machine
A state machine keeps track of where we are in a process so that it can easily go to the next step. Our state machine will keep track of loading numbers, sending each bit through for addition, and displaying the final results.
1) Open a new BDF called State_machine.
2) Add 3 D flip flops in a vertical column using the symbol tool. Leave 1 block of space between.
3) Add 3 2-input XOR gates to the left of each D flip flop. Less than a block of space is necessary, but leave some.
4) Using the orthogonal node tool, connect the output (right side) of each XOR gate to the D of the D flip flop directly to the right of it.
5) Add 2 2-input AND gates to the left and below the top two XOR gates.
6) Rotate each AND gate so that the 2 pins are facing upwards.
a) To rotate, click on the component
b) Right-click on the component to bring up a menu.
c) Choose an option to flip or rotate the component.
7) Connect one input from each AND gate to an input of the XOR gate right above it.
8) Connect the other input of each AND gate to the other input of the XOR gate right above it.
9) Connect the Q output from each D flip flop to one of the inputs of the XOR gate directly to its left.
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10) The output of the AND gates should connect to the input of the AND and XOR gate below it that isn’t connected to Q of the D flip flop.
Note: One XOR input is connected to Q from the D flip flop and the input from the AND gate. The other XOR input is connect to the other input from the AND gate and the output of the AND gate above it, if there is an AND gate above it.
11) For the 3rd XOR gate, one input will connect to the output of the AND gate above it.
12) The other input connects to the Q of the D flip flop to its right.
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13) Add the VCC pin.
Recommended placement is to the upper left of current components
14) Connect VCC to PRN of each D flip flop.
15) Add 3 input pins 3 blocks to the left of what we have so far.
16) Label the first input pin Control.
17) Connect the first input pin to the wire connecting the first XOR gate and the first AND gate.
Do not connect it to the wire that connects to the Q of the D flip flop.
18) Label the second input pin Clear.
19) Connect the second input pin to CLRN of each D flip flop.
20) Label the third input pin Clock.
21) Connect the third input pin to the clock input (triangle) of every D flip flop.
22) Add 3 output pins.
23) Label the first output pin Select1.
24) Connect select1 to Q of the first D flip flop.
25) Label the second output Select2.
26) Connect select2 to Q of the second D flip flop.
27) Label the third output pin select3.
28) Connect select3 to Q of the third D flip flop.
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29) Save the file.
30) Analyze the file.
31) Create a symbol for the file.
32) Add state_machine to the right of clock_generator in 4BitAdder.
STEP 4: 7-segment Display
We want our adder to look like a calculator too. Calculators display the numbers being added and their sum. To display our numbers on the board, our 7-segment display will take the binary representation of our numbers and display them on a typical digital number display.
1) Write out the numbers 0-9 in binary and how each number affects the lighting of each bar in the display.
Note: The bars are labeled A-G in a clockwise direction. Each output A-G will be affected by input 0000-1001. (Full 7-segment displays do 0-F using hexadecimal, 0-9 and A-F, but we will not require it. If you want to reuse this later, programming A-F is useful. I will be going over the full implementation of the 7-segment display.) In programming a 7-segment display, an output of 0 corresponds to a lit bar while 1 means it is not lit.
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2) Create a Verilog HDL file.
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This file will be different than the others. The output of each segment will be specifically spelled out in terms of binary. This file will be coded.
3) Save it as 7_segment_display.
4) In the first line, enter “module 7_segment_display(A, B, C, D, E, F, G, W, X, Y, Z);”.
Note: A-G are our outputs, corresponding to the 7 segments in the digital clock. W-Z are our inputs, corresponding to each digital of our binary numbers. These are case sensitive. Keep it the same.
5) On the second line, enter “input W, X, Y, Z;”.
6) For the third line, enter “output A, B, C, D, E, F, G;”.
7) On the fourth line, enter “reg A, B, C, D, E, F, G;”.
8) Skip to the sixth line.
9) Enter “always @(W or X or Y or Z)”.
10) On line 7, enter “begin”.
11) Line 8 will say “case({W, X, Y, Z})”.
Lines 6-8 will begin each case. Each case consists of the different possibilities for the inputs and what the output will be for each input.
12) Skipping to line 10, enter “4’b0000: A=’b0;”.
13) On line 11, enter “4’b0001: A=’b1;”.
“4’b” tells the computer that our inputs will be in 4 digits of binary, as opposed to decimal, hexadecimal, or octal. For each given input, the output of A is given, which can only have 1 decimal, corresponding to 2 possible outputs.
14) Use the input/output table that is shown above and that you made to complete the cases for output A.
15) After all the input cases are given, you should be ready to type on line 26.
16) On line 26, enter “endcase”.
17) On line 27, enter “end”.
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18) Skipping to line 29, begin the same process for output B.
19) To keep the code easy to read, keep spaces between the cases for each output.
20) If you kept spaces as suggested, when you are done with the cases for output G, the next empty line will be line 161.
21) On that empty line, enter “endmodule”.
22) Save the file.
23) Analyze the file.
24) Create a symbol for 7_segment_display.
STEP 5: Full_adder
The full adder is the device that does the actual adding in our entire program. The component takes in two bits and performs bitwise addition. Addition goes through first the 0’s place, then the 1’s place, and so on. If there is a carry from the previous place, it must be added in as well. A half adder does not consider the carry from previous mathematical operations.
1) Create a new BDF.
2) Save it as Full_adder.
3) Add 2 XOR gates to the file, side by side.
4) Add 2 2-input AND gates below the right XOR gate. The AND gates should be in a line vertically.
5) Add a 2-input OR gate to the right of the 2 AND gates, roughly between the two vertically.
6) Connect the output of one XOR gate to one input of the other XOR gate.
7) Connect that same wire to one input of the top AND gate.
8) Connect the other input of that AND gate to the other input of the right XOR gate.
9) Connect the outputs of the AND gates to the inputs of the OR gate.
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10) Add 3 input pins to the left of what we have, in a vertical line.
11) Label the top pin A.
12) Connect A to one input of the left XOR gate and to one input of the bottom AND gate.
13) Label the second pin B.
14) Connect B to the other input of the left XOR gate and to the other input of the bottom AND gate.
15) Label the third pin Ci (carry in).
16) Connect Ci to the wire connecting the input of the right XOR gate to the input of the top AND gate.
17) Add 2 output pins.
18) Label one Sum.
19) Connect Sum to the output of the right XOR gate.
20) Label the second Co(carry out).
21) Connect Co to the output of the OR gate.
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22) Save the file.
23) Analyze the file.
24) Create a symbol for full_adder.
STEP 6: Bringing It All Together
All of the smaller pieces of the 4 bit adder have been created. The parts we have left are to add the components in the necessary spots and then connect them together (the confusing part).
So far we have the clock_generator and state_machine in our 4BitAdder. (clock_generator should be somewhere to the left of our state machine.)
1) Add 8 16-input MUX (161MUX).
a) Expand the others folder under our default library.
b) Expand maxplus2.
c) Add the 16-input multiplexer.
2) Arrange the 8 MUXs into two rows, four long. They should be to the right of the state_machine (and therefore the clock_generator as well). It is easier if they are slightly below the state_machine.
a) The MUXs need to be rotated so that the one output is facing downward.
b) Leave 1 block of space between each MUX horizontally, and 3-4 blocks vertically between the two rows.
Each set of 4 MUXs take in inputs. The signal we send to selection inputs decides which signal will appear at the output.
3) Label the top set of MUXs RegA3-RegA0, from left to right, indicating bit 3-bit 0 for number A.
4) Label the bottom set of MUXs RegB3-RegB0.
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5) Add 8 D flip flops.
a) One flip flops should go below each MUX.
The D flip flops help to put the MUX onto the clock. Whatever signal is chosen by the MUX would be sent on its way, but by adding the flip flop, it will only be sent when the clock signal comes.
6) Add 4 7_segment_display.
a) All four will be to the right of MUX, with about 3 blocks of space between them and the MUX.
b) Two of the four will be above the MUXs, but still remaining to the right of them.
c) One of the 7_segment_displays will go between the two sets of MUXs.
d) The last one will go below the bottom set of MUXs.
The 7_segment_displays will help us see what is occurring in our circuit. One lets us see what numbers we will be putting into the circuit. Another tells us where the state machine is, with only 3 D flip flop, the choice go between 0 and 7. The last two displays of this group are just to make sure the circuit works correctly. The MUXs and D flip flops act as shifters; with the correct signal, the signal from one MUX will be sent to the one on its right. This also shifts the right-most bit into the adder later on. The 7_segment_displays will tell us what is coming out of each group of MUXs; this can be used to trouble-shoot any problems.
e) Label the top 7_segment_display as Number.
f) Label the 2nd display as StateMachine.
g) Label the 3rd display as RegA.
h) Label the 4th display as RegB.
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7) Add two more 16-input MUXs, one above the other, with the top’s output facing down, and the bottom’s output facing up.
a) These MUXs should be to the right and roughly in-between the other set of MUXs. (These MUX are also to the right of the 7_segment display for the top set of MUXs.
b) Label the top MUX AddBitA.
c) Label the bottom MUX AddBitB.
8) Add the full_adder to the right of the two AddBit MUXs, between them vertically.
9) Add a D flip flop to the right of the full_adder, place it about half a block lower.
10) Add 4 more 16-input MUXs to the right of the T flip flop. Leave 1 block of space between each component.
a) Label the MUXs RegC3-RegC0, left to right.
11) Add 4 D flip flops below each MUX.
12) Add a 7_segment_display to the right of the right-most flip flop.
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13) Connect output Q1 of the state_machine to SEL1 of every MUX.
14) Connect output Q1 of the state_machine to input Z of the 7_segment_display labeled StateMachine.
15) Connect output Q2 of the state_machine to SEL2 of every MUX.
16) Connect output Q2 of the state_machine to input Y of the 7_segment_display labeled StateMachine.
17) Connect output Q3 of the state_machine to SEL3 of every MUX.
18) Connect output Q3 of the state_machine to input X of the 7_segment_display labeled StateMachine.
19) Connect the output of every MUX to the D input of the D flip flop below it.
20) The MUXs labeled AddBitA and AddBitB should have their outputs connected to X and Y of the full_adder (one output to one input).
21) Connect the Q output of the D flip flop below RegA3 MUX to inputs IN0, IN2-IN5, IN14, and IN15 of the RegA3 MUX.
22) Also connect this same Q output to inputs IN6-IN13 of the RegA2 MUX.
23) Repeat steps 16 and 17 for the D flip flop below each RegA2-RegA0.
a) The Q output of the D flip flop for RegA2-RegA0 always connects to the same inputs of the register above it and to the right of it, just like RegA3.
b) For step 17 of the D flip flop below RegA0, Q connects to inputs IN6-IN13 of RegA3.
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24) Connect the Q output of the D flip flop below RegA3 to input W of RegA 7_segment_decoder.
25) Connect the Q output of the D flip flop below RegA2 to input X of RegA.
26) Connect the Q output of the D flip flop below RegA1 to input Y of RegA.
27) Connect the Q output of the D flip flop below RegA0 to input Z of RegA.
28) Connect the Q output of the D flip flop below RegB3 MUX to inputs IN0-IN2, IN4, IN5, IN14, and IN15 of the RegB3 MUX.
29) Connect the same output Q to inputs IN6-IN13 of RegB2 MUX.
30) Repeat steps 23 and 24 for D flip flop below RegB2-RegB0.
a) The Q output of the D flip flop for RegB2-RegB0 always connects to the same inputs of the register above it and to the right of it, just like RegB3.
b) For step 24 of the D flip flop below RegB0, Q connects to inputs IN6-IN13 of RegB3.
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31) Connect output Q of the D flip flop below RegB3 to input W of RegB 7_segment_decoder.
32) Connect output Q of the D flip flop below RegB2 to input X of RegB.
33) Connect output Q of the D flip flop below RegB1 to input Y of RegB.
34) Connect output Q of the D flip flop below RegB0 to input Z of RegB.
35) Connect the Q output of the D flip flop below RegC3 MUX to inputs IN0-IN4, IN14, and IN15 of RegC3 MUX.
36) Connect the same Q output of the D flip flop to inputs IN6-IN13 of RegC2.
37) Repeat steps 30 and 31 for each D flip flop below RegC2-RegC0.
a) The Q output of the D flip flop for RegC2-RegC0 always connects to the same inputs of the register above it and to the right of it, just like RegC3.
b) The Q output of the D flip flop for RegC0 does NOT connect to any inputs of RegC3.
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38) Connect output Q of the D flip flop below RegC3 to input W of RegC 7_segment_Decoder.
39) Connect output Q of the D flip flop below RegC2 to input X of RegC.
40) Connect output Q of the D flip flop below RegC1 to input Y of RegC.
41) Connect output Q of the D flip flop below RegC0 to input Z of RegC.
42) Connect output Q of the D flip flop below RegA0 to input IN6-IN15 of AddBitA MUX.
43) Connect output Q of the D flip flop below RegB0 to input IN6-IN15 of AddBitB MUX.
Note: The rest of these inputs and SEL0 for both of these MUXs will be left unconnected. This can cause problems in some circuits, but does not for this one. Be aware that if it does cause a problem, connecting the inputs to VCC or GND will often fix the problem. VCC is like 1, GND is like 0.
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44) Connect the output Sum of full_adder to inputs IN6-IN13 of RegC3 MUX.
45) Connect output Co of full_adder to the D input of the D flip flop to its right.
46) Connect the Q output of the D flip flop to the input Ci of the full_adder.
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47) Add 3 input pins to the left of all your components, one to the left of clock_generator, and the other two to the left of the state_machine.
48) Label the input to the left of the clock_generator Clock.
49) Connect it to the input of clock_generator.
50) Connect the output of clock_generator to the clock input of every D flip flop.
51) Connect the same output to the clock input of the state_machine.
52) Label one input pin to the left of the state_machine Control.
53) Connect Control to the input label control of the state_machine.
54) Label the third input pin Clear.
55) Connect Clear to the clear input of the state_machine.
56) Connect the same clear input pin to CLRN of every D flip flop.
57) Add 6 inputs pins above the RegA3 MUX.
58) Label the first input pin LoadA.
59) Connect LoadA to SEL0 of RegA3-RegA0.
60) Label the second input pin Bit3.
61) Connect Bit3 to IN1 of RegA3, IN3 of RegB3, IN5 of RegC3, and input W of the 7_segment_display labeled Number.
62) Label the third input pin Bit2.
63) Connect Bit2 to IN1 of RegA2, IN3 of RegB2, IN5 of RegC2, and input X of the 7_segment_display labeled Number.
64) Label the fourth input pin Bit1.
65) Connect Bit 1 to IN1 of RegA1, IN3 of RegB1, IN5 of RegC1, and input Y of the 7_segment_display labeled Number.
66) Label the fifth input pin Bit0.
67) Connect Bit0 to IN1 of RegA0, IN3 of RegB0, IN5 of RegC0, and input Z of the 7_segment_display labeled Number.
68) Label the sixth input pin Gn.
69) Connect Gn to the input GN of every MUX.
70) Add an input pin to the left of RegB3 MUX.
71) Label it LoadB.
72) Connect LoadB to SEL0 of RegB3-RegB0.
73) Add an input pin to the left of RegC3 MUX.
74) Label the pin LoadC.
75) Connect LoadC to SEL0 of RegC3-RegC0.
76) Add 7 output pins to the right of 7_segment_display labeled Number.
77) Label the outputs InputA-InputG.
78) Connect the output A-G of Number to their corresponding output pins.
79) Add 7 output pins to the right of 7_segment_display StateMachine.
80) Label the outputs StateMachineA-StateMachineG.
81) Connect outputs A-G of StateMachine to their corresponding output pins.
See Picture
82) Add 7 output pins to the right of 7_segment_display RegA.
83) Label the outputs RegAA-RegAG.
84) Connect the outputs A-G of RegA to their corresponding output pins.
85) Add 7 output pins to the right of 7_segment_display RegB.
86) Label the outputs RegBA-RegBG.
87) Connect the outputs A-G of RegB to their corresponding output pins.
88) Add 7 output pins to the right of 7_segment_display RegC.
89) Label the outputs SumA-SumG.
90) Connect the outputs A-G of RegC to their corresponding output pins.
See Picture
91) Save the file.
92) Click on Processing.
93) Go down to Start Compilation (this will take a few minutes).
The program may come up with a few warnings, but our circuit should still load to the FPGA correctly.
See Picture
STEP 7: Pin Assignments
Since we have finished the circuit of our project, we need to assign the input and output pins to switches and LEDs on the FPGA board. This will be the true test to see if the circuit works.
1) Click on Assignments.
2) Go down to Pin Planner.
A new window will appear with all the input and output pins you’ve placed in the circuit.
See Picture
3) Grab your FPGA manual or google your device’s pin assignment.
The pin assignment should go through all of your switches, LEDs, buttons, and 7 segment displays. The location of each will be given in the same row as it. (ex: PIN_N25)
4) Locate Bit0-Bit3 on the pin planner (should be alphabetical).
5) Select which switches you’d like to use for each pin (I used switch0-switch3 for Bit0-Bit3, respectively)
6) In your manual locate the switch you want to use and find its location ID.
7) In the pin planner, click in the location box and use the drop-down menu to select the correct location for that pin.
8) For your outputs, make sure the pin corresponds to the correct segment of the 7 segment display.
9) The input Clock should connect to an internal clock source. Make sure to use the one that has will scale correctly with your clock_generator.
Note: Make sure input pins are only switches and buttons. All of our outputs should be 7 segment displays.
Here is an example of what you could do.
• Switch0-3 for Bit0-Bit3.
• Switch 4 for LoadA
• Switch 5 for LoadB
• Switch 6 for LoadC
• Switch 7 for Control
• Switch 8 for Gn
• Switch 17 for Clear (since it resets the entire circuit, we try to keep it away from the switches we’d move more regularly)
• HEX7 for InputA-InputG
• HEX5 for StateMachineA-StateMachineG
• HEX3 for RegAA-RegAG
• HEX2 for RegBA-RegBG
• HEX0 for SumA-SumG
10) After your pins are assigned, exit out of the pin planner.
11) Re-compile the circuit.
a) Processing->Start compilation
12) Make sure your FPGA is hooked up to its power.
13) Make sure your FPGA is attached to the USB.
14) Turn on your FPGA.
15) Back in Quartus, go to Tools.
16) Go down to Programmer and click.
17) Click on the Hardware Setup button.
18) Select the USB blaster.
19) Click Start.
All of the 7 segment displays that are being used should show up as 0, if all of your switches are off.
To use your adder:
1) Turn the switch corresponding to Clear on.
This seems counter-intuitive, but the way it is used in the circuit, the clear must be 1 in order for the circuit to function.
2) Use the switches corresponding to Bit3-Bit0 to select a number you want. The number should appear in one of the displays.
3) Flip the switch for LoadA. (This may take a few seconds).
4) After the number shows up in a second 7 segment display, flip switch for LoadA off.
5) Select your next number for Bit3-Bit0.
6) Flip switch for LoadB.
7) Flip the switch for control.
8) The display for StateMachine should increase from 0 to 1 within a few seconds, when it does, turn the switch for control off.
9) Turn the switch for LoadB off.
If your set-up is like mine, your two numbers for A and B will be displayed beside each other. We could also load a number into C, which is the sum of A and B, but we won’t bother since we want to see addition take place.
10) Turn the control switch back on.
11) Let it run until the StateMachine hits 7, then turn it off.
12) The final display should show you the sum of your two numbers!
As the calculator runs, you will see your two numbers changing as the bits shift through the registers and end up in different MUXs.
Now that your adder works, you can add it to other projects or adjust it so that it does subtraction or even multiplication. Overall, I hope you see the complexity of something that sounds so easy. If you have any questions for me about my project, or possibly about other circuits, email me at adp1@iastate.edu.
2 Comments
Ray98 3 years ago
desmondtheredx 10 years ago
would you know how to write a VHDL file for this?