Connect Camera to Zedboard

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The Zedboard is a powerful hobbyist system on chip with a ARM Coretx-A9 processor and a Xilinx FPGA built in. A great addon for the Zedboard is the OV7670 camera for image and video processing. The OV7670 can output 12 bit RGB in 640x480 resolution at 30 fps and can purchased for less than $20. The OV7670 camera used for this tutorial can be found here.

This tutorial will show you how to connect the OV7670 camera to the Zedboard and stream the camera through the VGA port on the board. The VHDL modules allow for easy interface to the frame information for further image processing.

A datasheet for the OV7670 is attached.

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Step 1: Import VHDL Code

The first step is to install Vivado 2015 on your computer and create an RTL project using the ZedBoard Zynq Evaluation and Development Kit. Next thing to do is to download all of the VHDL files attached to this step then add them to the project by clicking Add Sources under Project Management. If everything has been added correctly you should see the ov7670_top file under Design Sources and then all of the over various VHDL sources underneath it.

Step 2: Add Block Memory

The frame of the image is stored in a piece of block ram. To add the block ram to the project, click on the IP catalog under Project Manager and search for Block Memory Generator. The settings of the block ram can be seen in the images attached.

Step 3: Add Constraints File

To connect the FPGA to the camera a constraints file defining the inputs and outputs has to be declared. To add the constraints file, click on Add Sources then Add Constraints then import the XCF file connected. After the XCF file is imported the camera has to be connected. The XCF file lists all of the net names of the FPGA pins and the connections to the camera. You must connect the camera pins to the FPGA pins by using the PMOD/Pin table and the PMOD pinout.

Step 4: Generate Bitstream

Now the final step is to generate the bit stream by clicking Program and Debug then Generate Bitstream and connect the Zedboard to a monitor through the VGA port. After the bitstream has been generated and uploaded to the FPGA you should see the camera streaming on the monitor. Make sure to take the lens off the camera and to focus the camera!

The implementation guide attached describes the register settings in the camera to change various settings. To change the camera settings the ov7670_registers.vhd file must be edited. To decrease resource utilization, the camera can be changed to output only YUV and record the Y component which would store a greyscale version of the image which would reduce the memory block width from 14 bits to 8 bits.

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    10 Discussions

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    panteha100

    3 months ago on Introduction

    I don't know how to connect camera OV7670 to the Zedboard? can anyone help me please

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    Bhargav12

    6 months ago

    Hello!
    I am trying to implement the above code on my Zedboard, the camera output is displayed on the board but it isn't very clear! Could anyone please help me with some modified Register settings for the same camera OV7670.
    Thank you in advance!

    2 replies
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    ananthamarBhargav12

    Reply 4 months ago

    hello!!!! just adjust the lens of your camera
    rotate the lens in anti clock wise till the streaming looks better.
    enjoy!!!!!!!!!

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    ananthamarBhargav12

    Reply 5 months ago

    i too implemented the project. but the output is not clear like your output. i've made some changes to the ov7670 register settings..but it is useless... if u find anything useful kindly let me know that modification u made...... thank you.

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    ananthamar

    Question 7 months ago

    hi there!!! can anybody share the step by step process for this project...???

    thanks in advance

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    sus_singh

    1 year ago

    How to connect power and GND pins? I think there is 1 mistake, JA3 should be connected to Y10. Please confirm.

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    ApoorvU2

    1 year ago

    I want use my pc camera for image processing. Please tell me steps to do that.

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    TerryC132

    2 years ago

    Can't read the Memory block settings. Pressing Download requires going Premium...

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    KevinH215

    3 years ago

    Hi I was interested in trying this project. When I attempt to synthesize the project I receive an error. Any ideas on how to get around this?



    • [Synth 8-549] port width mismatch for port 'addra': port width = 18, actual width = 19 ["C:/Users/Khugh/OneDrive/Documents/embedded_systems/final/fivenine/ov7670_top.vhd":144]
    0
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    wold630

    3 years ago

    Lots of great info, thanks!