Introduction: Design of I2C Master in VHDL
In this instructable, Designing a simple I2C interface in VHDL is discussed.
NOTE: click on each image to see full image.
Step 1: What Is I2C
•Stands for Inter Integrated Circuit.
•Synchronous , Half duplex.
•Two Wire Interface - SDA and SCL.
•SDA – controlled by both Master and Slave.
•SCL – controlled only by Master.
•Multi-master , Multi-slave protocol.
•Two modes - 100 kbits/sec and 400 kbits/sec : slow and fast.
Step 2: Designing in VHDL
- 8-bit data frame.
- 7-bit slave address.
- Supports both slow and fast modes.
- Single Master, Multi-slave.
- Main clock input = 100 MHz.
Step 3: Simulation and Testing
- Implemented on Altera Cyclone III FPGA.
- Timing verified for 100 MHz.
- Tested waveforms on DSO/CRO.
- Successfully tested communication with Arduino UNO's I2C (FPGA as Master).
Simulation was done in Modelsim 10.1.
Step 4: Important Notes
- Input clock is 100 MHz. In case, you have different crystal clock in FPGA, either use PLL to generate 100 mHz or carefully edit the clock divider process accordingly in i2cmaster.vhd. As it is responsible to generate 400 kHz or 100 kHz i2c clocks.
- In case of error in communication, i2c master goes to error state. Assert stop signal '1' to generate stop bit and restart communication.
- While testing, dont forget pull-up resistors as SDA line is common drain output !!! Check google for recommended pull-up resistor for different i2c speeds. I used 2.2K.
- Carefully simulate SDA signal, as it is a bi-directional signal (inout) signal. It has two drivers, master side and slave side. You should know when to 'force' and when to 'unforce'.
- SCL is unidirectional line. No need of pull-up.
- chip_enable is active low in the attached code, unlike in the simulation waveform.
Step 5: Files Attached
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