Design of SPI Master in VHDL

About: Mitu Raj - Just a Hobbyst and Learner

In this instructable, you are going to design an SPI Bus Master in VHDL.

Step 1: Overview of SPI

  • SPI is a Synchronous Serial Bus.
  • Full Duplex.
  • Among the fastest Buses.

Step 2: Design Specifications

These are the specs of the SPI Master we are gonna design.

  • Two modes of operation - Mode 0, Mode 1.
  • 8-bit data frame.
  • Synchronous, full duplex with one cycle inter-frame latency.
  • Interrupt generated for each data frame.

Step 3: RTL View of the SPI Master Core and Simulation Waveforms

Check out the RTL View of the IP core ( click to see full image).

Check out the simulation waveforms.

Step 4: Test Environment

  • Tested on Altera Cyclone III FPGA, with timing verified up to 400 MHz Main clock input.
  • SPI clock speed (SCL) designed @ 12.5 MHz for 100 MHz Main clock input (divide factor = 8).
  • Tested SPI Master @Clock speed 4 MHz with Arduino UNO as slave.
  • Tested waveforms in DSO.

Step 5: Notes

  • Active low asynchronous reset signal.
  • Active low synchronous chip enable signal.
  • Active low slave selectsignal, selects slave on falling edge.
  • SPI Modes in compliance with Texas SPI specifications - Mode 0, Mode 1.
  • Note the simulation waveforms, to see how to simulate the design.

Step 6: Files Attached

  • Main VHD file for SPI Master
  • Testbench for functional simulation.

for queries:

contact -- iammituraj@gmail.com

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