Design of UART in VHDL

Introduction: Design of UART in VHDL

About: Mitu Raj - Just a Hobbyst and Learner

UART stands for Universal Asynchronous Receiver Transmitter. It is the most popular and simplest serial communication protocol.In this instructable, you will learn how to design a UART module in VHDL.

Step 1: What Is UART ?

To communicate with various peripherals, the processors or controllers usually use UART communication. It is a simple and fast serial communication. Since UART is a minimum requirement in almost all processors , they are usually designed as Soft IP cores in VHDL or Verilog for re-usability and ease of integration.

Step 2: Specifications

The specifications of the designed UART are given below :

* Standard interface signals.

* Configurable baud rate from 600-115200.

* FPGA proven design - on Xilinx Artix 7 board.

* Can be easily integrated with processor cores as soft IP.

Step 3: Simulation Results

Step 4: Attached Files

* UART transmitter module -vhd file

* UART receiver module - vhd file

* Baud generator module - vhd file

* UART module - The main top module integrating the above modules - vhd file

* Full documentation of the UART IP Core - pdf

Designed By : Mitu Raj

For queries, Contact : iammituraj@gmail.com

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    6 Discussions

    hwo we can get password ?

    thank you for sharing. could you send me the password for the zip, please?

    2 replies

    Thanks for sharing the file. i'm working on CNC project that uses UART to communicate with the PC. could you please send me the password for the zip file at shenobet@gmail.com

    1 reply