Introduction: Design of UART in VHDL
UART stands for Universal Asynchronous Receiver Transmitter. It is the most popular and simplest serial communication protocol.In this instructable, you will learn how to design a UART module in VHDL.
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Step 1: What Is UART ?
To communicate with various peripherals, the processors or controllers usually use UART communication. It is a simple and fast serial communication. Since UART is a minimum requirement in almost all processors , they are usually designed as Soft IP cores in VHDL or Verilog for re-usability and ease of integration.
Step 2: Specifications
The specifications of the designed UART are given below :
* Standard UART signals.
* Configurable baud rate from 600-115200.
* Sampling = 8x @receiver
* FPGA proven design - on Xilinx Artix 7 board.
* Tested on UART peripherals, Hyperterminal successfully - all baudrates
Step 3: Design Approach
- We will be designing 3 modules, which we will integrate later on to complete the UART.
- Transmitter Module: Takes care of serial data transmissions
- Receiver Module: Takes care of serial data receptions
- Baud generator Module: Takes care of baud clock generation.
- Baud generator module is dynamically configurable. It generates two baud clocks from main clock, according to the desired speed. One for transmitter, other for receiver.
- Receiver module uses an sampling rate of 8x to minimise the probability of error in reception, ie., receiver baud clock is 8x transmitter baud clock.
- Control signals to control transmission and reception, as well as interrupt signal.
- Standard UART serial interface with no parity bit, one stop and start bit, 8 data bits.
- A parallel interface to communicate with host ie., a processor or controller, who feeds and receives parallel data to and from UART.
Step 4: Simulation Results
Step 5: Attached Files
* UART transmitter module -vhd file
* UART receiver module - vhd file
* Baud generator module - vhd file
* UART module - The main top module integrating the above modules - vhd file
* Full documentation of the UART IP Core - pdf
Designed By : Mitu Raj
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