Design of UART in VHDL

Introduction: Design of UART in VHDL

About: Mitu Raj -- Just a Hobbyst and Learner -- Chip Designer -- Software Developer -- Physics and Mathematics Enthusiast

UART stands for Universal Asynchronous Receiver Transmitter. It is the most popular and simplest serial communication protocol.In this instructable, you will learn how to design a UART module in VHDL.

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Step 1: What Is UART ?

To communicate with various peripherals, the processors or controllers usually use UART communication. It is a simple and fast serial communication. Since UART is a minimum requirement in almost all processors , they are usually designed as Soft IP cores in VHDL or Verilog for re-usability and ease of integration.

Step 2: Specifications

The specifications of the designed UART are given below :

* Standard UART signals.

* Configurable baud rate from 600-115200.

* Sampling = 8x @receiver

* FPGA proven design - on Xilinx Artix 7 board.

* Tested on UART peripherals, Hyperterminal successfully - all baudrates

Step 3: Design Approach

  1. We will be designing 3 modules, which we will integrate later on to complete the UART.
    • Transmitter Module: Takes care of serial data transmissions
    • Receiver Module: Takes care of serial data receptions
    • Baud generator Module: Takes care of baud clock generation.
  2. Baud generator module is dynamically configurable. It generates two baud clocks from main clock, according to the desired speed. One for transmitter, other for receiver.
  3. Receiver module uses an sampling rate of 8x to minimise the probability of error in reception, ie., receiver baud clock is 8x transmitter baud clock.
  4. Control signals to control transmission and reception, as well as interrupt signal.
  5. Standard UART serial interface with no parity bit, one stop and start bit, 8 data bits.
  6. A parallel interface to communicate with host ie., a processor or controller, who feeds and receives parallel data to and from UART.

Step 4: Simulation Results

Step 5: Attached Files

* UART transmitter module -vhd file

* UART receiver module - vhd file

* Baud generator module - vhd file

* UART module - The main top module integrating the above modules - vhd file

* Full documentation of the UART IP Core - pdf

Designed By : Mitu Raj

For queries, Contact : iammituraj@gmail.com

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    39 Discussions

    0
    EEE_student
    EEE_student

    6 weeks ago

    can u please send me the password?

    0
    AmCoder
    AmCoder

    Reply 5 weeks ago

    sure

    0
    AmCoder
    AmCoder

    Reply 2 months ago

    sure

    0
    s91aif
    s91aif

    Question 3 months ago

    thanks, plase password

    0
    SteveAZ
    SteveAZ

    4 months ago

    Hello I am a retired engineer and now hobbyist could you please send me the password to your zip file? I would like it to make a UART to communicate with my telescope. Thank you. Steve Clauter, steveclauter@gmail.com

    0
    PayamS2
    PayamS2

    4 months ago

    hi im a student and i really need the code, can you please send me the code?
    my eamil is psedighiani@yahoo.com

    0
    ragdent
    ragdent

    5 months ago

    could you share me your password please?
    thanks

    0
    AmCoder
    AmCoder

    Reply 5 months ago

    sure

    0
    zhouyk123
    zhouyk123

    5 months ago

    Hi i am student, could you please send me the password for the zip to zhouyk12@gmail.com. Thanks a lot.

    0
    AmCoder
    AmCoder

    Reply 5 months ago

    sure

    0
    xc7v2000t
    xc7v2000t

    6 months ago

    Thank you for sharing the code! May I have the password? Thank you very much and have a nice day! My email is ligeng19901003@gmail.com