The Arty is a versatile FPGA development board that is able to implement the softcore processor MicroBlaze. This IP core allows programming of the FPGA with the Xilinx SDK.
Step 1: Create a New Project
Create a new project in Vivado with the following properties:
- Name with no spaces
- RTL project
- Check the Do not specify sources at this time
- Select Arty from the Boards section as in the image above
NOTE: When naming your project make sure that there is no spaces in the Project Name or Project Location (also known as the path). If there are spaces the SDK will not be able to open the project later.
Step 2: Create a Block Design
From the left pane create a block design and name it whatever you like, again no spaces.
Step 3: Add Clock Management
Adding IP to the block design is as simple as dragging and dropping the items from the available IP into the Diagram pane. Add the System Clock IP to the design by this method. To configure the Clocking Wizard double click on the block. Under the Output Clocks tab set clk_out1 to 166.667 MHz and clk_out2 to 200 MHz. Also set the Reset type at the bottom of the pane to be Active Low. Click OK. A green banner should appear saying that you can run connection automation, do so.
Step 4: Add Memory
As in the previous step add the DDR3 SDRAM. Delete the clk_ref_i and sys_clk_i signals that are created and reconnect them to clk_out2 and clk_out1 of the Clocking Wizard respectively. Run connection automation again.
Step 5: Adding the Processor
Click the Add IP button as shown above to open the IP catalog and search for MicroBlaze. Drag and drop the MicroBlaze item into the design. Now run block automation selecting the Clock Connection to /mig_7series_0/ui_clk. Select any memory size for the Local Memory and Cache Configuration. Once this is complete do not run the connection automation yet.
Step 6: Add LED and Switch Peripherals
Next add the 4 LEDs and 4 Switches GPIO IP blocks the same way as the Clocking Wizard and Memory. Run the Connection Automation. When the dialog appears select All Automation and click OK. The block design is almost complete.
Step 7: Regenerate and Validate
Regenerate the block design. This will rearrange the blocks into a cleaner layout. Now Validate the design. This will check for errors in the design.
Step 8: Create HDL Wrapper and Generate the Bitstream
In the sources tab right click on the block design and select Create HDL Wrapper. A dialog will pop up, ensure that the Let Vivado manage wrapper and auto-update is selected. Hit OK. Now generate the bitstream as normal, this may take some time.
Step 9: Export to Xilinx SDK
Now that the bitstream has been generated export the hardware with File->Export->Export Hardware, check the Include Bitstream box when the dialog pops up. This will generate some files that the SDK will use to generate its binaries. Next open the SDK with File->Launch SDK.
Step 10: Write the Program for the Processor
Once the SDK is open create a new Xilinx Application Project with a name of your choosing. This will generate two project folders in the Project Explorer pane. Expand the blue one and right click on the src folder. Select New->Source File. In the Dialog Box call the file main.c. Copy the contents of the main.c file below into the new file. Look at the block design, if the AXI GPIO block looks like the one above then you don't need to edit the program. Otherwise change the #define lines so that LED_CHANNEL is 2 and SW_CHANNEL is 1.
Step 11: Program the FPGA
In order for the program to be run on the board the FPGA must be programmed with the bit file from earlier. To do this click on the Program FPGA button.
Step 12: Program the Processor
Finally we can program the processor with our code. To do this click on the drop-down menu by the Run button and select Run As->Launch On Hardware (System Debugger).
The board is now programmed! Flipping the switches should turn on and off the corresponding LEDs.