I have done this simulation project for an online class. The project is written by Verilog. We will use simulation in Vivado to visualize the waveform in enable_sr(enable digit) from the stop watch project previously created. In addition, we will use the system task to display error made by us in the design.

Step 1: Add Sources and Choose “Add or Create Simulation Sources

Step 2: Create File Called Enable_sr_tb

Step 3: Create Testbench File

1. Import the module enable_sr from stop watch project. That is the file we want to simulate

2. Create testbench module enable_sr_tb();

3. Key in inputs and outputs of the module enable_sr(). Remember the inputs for enable_sr is now in register type while the outputs become net type.

4. Instantiate the unit under test (uut) which is the enable_sr

5. Generate clock which period (T) is 20ns

6. Use the conditional statement to create error checking system. In this example, we want to check whether there are more than one digits are active.

Note: In the original enable_sr() file, we should initial the pattern as 4’b0011 so that there are two digits are active to create error.

7. Use system task $display to show the error

8. Use system task $finish to complete the simulation at time 400ns

Step 4: Set the Enable_sr_tb As the Top Level Under the Simulation

Step 5: Run Synthesis & Behavioral Simulation

Before running behavioral simulation, run the synthesis to make sure that there isn't any syntax errors in the testbench file and unit under test file
Run the behavioral simulation