System will use a microphone array and Time-Difference-of-Arrival (TDoA) approach to determine the direction of a sound source in real-time. User can see his/her own position and direction of the signal source on a satellite map using a graphical user interface.
Microphones are synchronously sampled and resulting signals go through various filtering stages to ensure the signal source is the desired one. Amplitude peaks and phases of signals are then measured to get time difference of arrival between microphones. Direction of the incoming sound signal is then determined by vector processing using time differences and known shape of the microphone array. These stages will run on the ZYNQ's Artix-7 FPGA subsystem. Linux environment will be used for GUI and a satellite map showing the direction of the source. Linux environment will run on the ZYNQ's ARM Cortex SoC. Pmod GPS receiver will be used to pinpoint device location. Pmod MIC3 MEMS microphones will be used for the microphone array. ZYBO board is the development platform.
Bill of Materials
- Zybo Zynq-7000 ARM/FPGA SoC Trainer Board
- 5 x Pmod Mic
- Pmod Gps
- SD card 4GB or higher
- SD card reader
- Monitor with HDMI
- Keyboard and mouse
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Step 1: Setting Up Development Enviroment
1. Installation Vivado
You can download and easily install Vivado from https://www.xilinx.com/products/design-tools/vivad... you should have at least web pack licence for this project.
2. Creating bootable sd card with Xillinux
Go this link and download sd card image http://xillybus.com/xillinux . Image file should be writen with to sd card using image writer tools. In this case, Win32 Disk Imager is used.
Step 2: Creating Vivado Project Workable With Xillinux
1. Creating project using Tcl Script
http://xillybus.com/xillinux go this address and dowload xillinux-eval-zybo-2.0a.zip for Zybo board. Extract it and open Vivado. Find tcl script in verilog folder and run it using tcl console. After the Tcl script operation is done, your project is created.
2. Disabling showstopper.tcl
Project Settings> Implementation > Route Design : find showstopper.tcl and disable it. Show stopper tcl is a script which controls the timming in projects that contain Linux core. If costum design logic is added to fpga part, this script is suggested to disable.
3. Compiling code and run on Zybo
After compilation finish, ".bit" file is found in project folder and it is copied to SD card which is early loaded with Xillinux.
Step 3: Pmod Mic Driver
Pmod mic is a module which contains mems microphone and ADC to read that microphone. ADCS7476 is the ADC module inside it. To work with this module driver software is writen in verilog. ADCS work with a basic SPI communication. "PmodMic3.v" is a module that handles the state machine to get data from microphone.
Step 4: Communication With Linux Core of Zybo
One of the main problem communication with Linux core was the clock difference of the writen modules. Xillybus which is enable fpga part communicate Linux core, works at frequency of 125 mhz. Microphone controller is work on 1 mhz. To solve this problem a fifo is added between this two module. This fıfo has 2 different clocks for its input and output.
Step 5: Posistioning Algorithm
Multilateration algoritm is used for posistinıng. Multilateration uses time difference of arrival of a signal. The principle is that a signal will arrive at different locations at slightly different times. The system is designed to capture four of these times at different receiver locations. Each of the travel times of a signal to these locations is simply the distance formula divided by the speed of sound.