Introduction: Wishorrelator

  1. fulfillment of wishes

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Step 1: Introduction

This device has emerged as an idea to materialize wishes. The principle of operation is as follows: At the time when the thought of wish press the button to capture the moment in a pseudo random number.Random number is three-dimensional vector size of 24 bits. In order to distinguish when transmitting, each vector is represented by a different color.Each of the outputs is then presented in all three dimensions (color), so you get a complete sphere. Now that we are wish to materialize, we have to broadcast into space for some time to cause a curvature of space and time towards the fulfillment of wishes. Button on the side choose the speed at which will be broadcast sequence. The device is left in place to sleep or stay and wait for that to happen correlation between desire and reality.

Step 2:

This is how it looks when the unit operates !!!

Step 3: Construction

Whole arrangement was made about cheap Chinese development boards with Altera CPLD EPM240T100C5 circuit. Intentionally libraries were used is standard TTL logic gates. If someone wants to do with such logical gates can very easily using an electric circuit. It is also given Quartus II 8.1 project if you want something to change.It is very important that the keys SW1, SW2 and SW3 are mechanically connected to simultaneously switch ON.

Step 4:

That's all! This is normally part of a larger project which will be presented with Extra low frequency widespread with frequency hooping technique to analyze the EM signals in the human body.

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    2 Discussions


    5 years ago on Introduction

    I need one of these!

    Do you have a list of wishes you've been granted? :)


    Reply 5 years ago on Introduction

    No, unfortunately wish list is entered as a text file on the SD card. File system is wishFATe (j * x!) Where x = -1 for morning wishes, x = 1 for the afternoon wishes and x = 0 for the wish at noon. List should be arranged upside down because it has been used LIFO stack. For CPLD integrated circuit is no place for SD support so that plans for FPGA version.