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I work in the Digilent sales team and promote engineering education hardware to students, educator or who wants to learn engineering and technology. I like learning the new technology and hope people understand that engineering is not around us.
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- alexwonglik's instructable UART communication on Basys 3, FPGA dev board powered by Xilinx Artix 7 Part I's weekly stats: 2 years ago
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- alexwonglik's instructable UART communication on Basys 3, FPGA dev board powered by Xilinx Artix 7 Part II's weekly stats: 2 years ago
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- alexwonglik's instructable Debonucing Button on Basys 3, Xilinx FPGA Development Board's weekly stats: 2 years ago
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- alexwonglik posted an instructable Debonucing button on Basys 3, Xilinx FPGA Development Board2 years ago
- alexwonglik posted an instructable Sequence Detector using Digilent Basys 3 FPGA board3 years ago
- alexwonglik commented on alexwonglik's instructable How to use Verilog and Basys 3 to do stop watch3 years agoView Instructable »
Then, you should have another for loop to create another clock in the clock divider. And you need to assert that signal in the counter module and add another condition. And in the top module, you should add condition to trigger either counter
