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how can we design wireless "Low Frequency" digital audio reciever implemented in fpga? Answered


Wireless is radio - "low frequency" is the kicker. Standard AM tops out at 1.5MHz, amateur shortwave or HF reaches 30MHz (HF CB Radio). That gives to 2 approaches.

First Approach: Get a fast Analog-Digital Converter (ADC) chip. Linear Technology and Texas Instruments have ADC's running at 65M samples/sec (Msps) . Once the RF is in the FPGA, use DSP techniques to isolate the frequency you want. Problem: the pre-built Dev Kits with a suitable ADC are NOT Cheap!

Second Approach: Make a basic converter to get a section of RF down to near DC. You can use slower ADC, but due to the vagaries of mixing you will have "negaive" or host channels unless you add a second ADC. Look up "IQ" sampling for more details.

THis isn't the place to ask. Find a forum for your specific family of FPGAs. What are you using ? Altera ?

we just wanted the design concept/block diagram for it.we are using spartan 3E