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# verilog code ?

I have made sample code for 4 bit ALU and 3 to 8 decoder to make 4 bit processor . as designer we can design anything so I have started to design processor with two function ALU and decoder

4 bit alu

Module alu (a,b,s0,s1,s2 f);

Input a,b,s0,s1,s2;

Output f;

Reg [3:0];

Always @(s0,s1,s2);

Begian

Case (s0,s1,s2);

3b’000 :f=(a&b);

3b’001:f= (a|b);

3b’010 :f= ~(a&b);

3b’011 :f= ~ (a|b);

3b’100:f=(a^b);

3b’101: f=(a*b);

3b’110: f=(a+b);

3b’111:f=(a-b );

End case

End module

3to 8 decoder

Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);

Input a2,a1,a0;

Output d7,d6,d5,d4,d3,d2,d1,d0;

Wire [7:0];

Always @(a2,a1,a0);

Begin

Case (a2,a1,a0);

4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;

4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;

4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;

4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;

4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;

4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;

4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;

4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;

Endcase

Endmodule

I don't understand how to connect 4 bit Alu with

3 to 8 bit decoder to make 4 bit processor

4 bit alu

Module alu (a,b,s0,s1,s2 f);

Input a,b,s0,s1,s2;

Output f;

Reg [3:0];

Always @(s0,s1,s2);

Begian

Case (s0,s1,s2);

3b’000 :f=(a&b);

3b’001:f= (a|b);

3b’010 :f= ~(a&b);

3b’011 :f= ~ (a|b);

3b’100:f=(a^b);

3b’101: f=(a*b);

3b’110: f=(a+b);

3b’111:f=(a-b );

End case

End module

3to 8 decoder

Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);

Input a2,a1,a0;

Output d7,d6,d5,d4,d3,d2,d1,d0;

Wire [7:0];

Always @(a2,a1,a0);

Begin

Case (a2,a1,a0);

4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;

4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;

4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;

4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;

4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;

4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;

4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;

4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;

Endcase

Endmodule

I don't understand how to connect 4 bit Alu with

3 to 8 bit decoder to make 4 bit processor

## Discussions

I have made table for decoder and ALU

4 bit ALU

S2 S1 S0 F

0 0 0 F= A and B

0 0 1 F= A or B

0 1 0 F= A Nand B

0 1 1 F= A nor B

1 0 0 F= A Xor B

1 0 1 F= A X nor B

1 1 0 F= A addition B

1 1 1 F= A subtraction B

S2 S1 S0 A B F

0 0 0 0 0 0 AND logic

0 1 0

1 0 0

1 1 1

0 0 1 0 0 0 Or logic

0 1 1

1 0 1

1 1 1

0 1 0 0 0 1 NAND

0 1 1

1 0 1

1 1 0

0 1 1 0 0 1 NOR

0 1 0

1 0 0

1 1 0

1 0 0 0 0 0 Xor

0 1 1

1 0 1

1 1 0

1 0 1 0 0 1 Xnor

0 1 0

1 0 0

1 1 1

1 1 0 0 0 0 addition

0 1 1

1 0 1

1 1 0

1 1 1 0 0 0 subtraction

0 1 1

1 0 1

1 1 0

Appears as the table includes improbable 6 bit wide data on a 4 bit ALU.

If the processor hardware design is to include a combination of instruction and data wider then the ALU surely make it a multiple of 4 bits.

data register is 4 bit

instruction register is 4 bit

So including NOP you have 15 other instructions.

AND,OR,ADD,SUB,ROTATE,NOT,NAND,NOR,XOR,JUMP,SKIP=,SKIP>,SKIP>,SKIP<>,SKIPonCARRY,SET,CLEAR

thats ok but how to write verilog code I mean I can write code for ALU , decoder , counter but how to write for processor

I have to write like this

module processor (input output )

input ;

output.;

always @(posedge);

endmodule

or I have to write like this

module processor (input output )

input ;

output.;

always @(posedge);

module ALU (input output )

input ;

output.;

always @(posedge);

endmodule

module decoder (input output )

input ;

output.;

always @(posedge);

endmodule

module counter (input output )

input ;

output.;

always @(posedge);

endmodule

module register (input output )

input ;

output.;

always @(posedge);

endmodule

endmodule

Connect physically or via as yet unsubscribed instructions ?

You seem to be describing bitwise ALU operations

You need to incorporate a 4 bit lookup table and implied address jumping using a flag to output 8 bit info on a 4 bit ALU as two sequential 4 bit words.

data register is 4 bit wide

and instruction register is 4 bit wide

Will really help you - The book as well

+1