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Again, you might want to explain the difference between LS and standard ICs. The faster you push a signal through a gate, the more the output looks like a sine wave and the specification has not only rise and fall time but voltage threshold requirements too. That is how I. C.s are tested ( and a lot may fail at the manufacturing plant ).
You might want to add a description and why LS devices are used instead of regular ICs like the 7404. There is also a Sample and Hold circuit in place that holds data until the system clock triggers the IC. Also, the fact at original 1 GHz clock speeds, a digital 1 and 0 starts looking like a sine wave and the talk is about threshold voltages and duration for a 1 and 0. ( that is how a PIN ELECTRONIC card is calibrated for mass IC test systems ). I know, because I became a senior Calibration Tech ( there were no Test Engineer Degrees in those days ) and worked on the bleeding edge of technology for many years.I was formally trained in microelectronics by a fellow engineer/scientist at the Chippewa Falls Technical School. This training helped me to understand failure modes for ICs and why ESD causes failures. I may not be aware of how our custom gate arrays worked but I can tell people what failure modes were on a failed part!P.S. the metallic substrates and insulating substrates deposited on the silicon ( sand or glass ) do the actual conducting and semi conducting. the wafer base material ( even diamond! ) does not. Think of the wafer base material as a foundation of the " building " you are creating. If you want to really scare people, you could describe how the layers of the actual semiconductor are created. For people who know a bit about chemistry, looking at a standard chart of the elements will explain why these chemicals are used in semiconductors.
I will add some other issues just to stir everything up. At Cray Research, some of us used NMOS semiconductors internally with ECL outputs and others, like Seymour, used complete ECL only devices. I'm sure our expert knows WHY these ECL connections were used. The original X-MP used 16 gate arrays, custom made in our silicon foundry and were sent out to be mass produced. The bad news: U.S.suppliers could not meet our speed specifications; other engineers and myself got sent out to train U.S. suppliers how to build faster gate arrays. The two Japanese suppliers had no problem in meeting our specifications. Two years later, both Japanese companies showed up with supercomputers of their own. So much fr the NDAs both companies signed...8-/.
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