Step 8: IO port expansion, more multiplexing
We gathered from the last step that an 8x8x8 LED cube requires 64+8 IO lines to operate. No AVR micro controller with a DIP package (the kind of through hole chip you can easily solder or use in a breadboard, Dual Inline Package) have that many IO lines available.
To get get the required 64 output lines needed for the LED anodes, we will create a simple multiplexer circuit. This circuit will multiplex 11 IO lines into 64 output lines.
The multiplexer is built by using a component called a latch or a flip-flop. We will call them latches from here on.
This multiplexer uses an 8 bit latch IC called 74HC574. This chip has the following pins:
- 8 inputs (D0-7)
- 8 outputs (Q0-7)
- 1 "latch" pin (CP)
- 1 output enable pin (OE)
The job of the latch is to serve as a kind of simple memory. The latch can hold 8 bits of information, and these 8 bits are represented on the output pins. Consider a latch with an LED connected to output Q0. To turn this LED on, apply V+ (1) to input D0, then pull the CP pin low (GND), then high (V+).
When the CP pin changes from low to high, the state of the input D0 is "latched" onto the output Q0, and this output stays in that state regardless of future changes in the status of input D0, until new data is loaded by pulling the CP pin low and high again.
To make a latch array that can remember the on/off state of 64 LEDs we need 8 of these latches. The inputs D0-7 of all the latches are connected together in an 8 bit bus.
To load the on/off states of all the 64 LEDs we simply do this: Load the data of the first latch onto the bus. pull the CP pin of the first latch low then high. Load the data of the second latch onto the bus. pull the CP pin of the second latch low then high. Load the data of the third latch onto the bus. pull the CP pin of the third latch low then high. Rinse and repeat.
The only problem with this setup is that we need 8 IO lines to control the CP line for each latch. The solution is to use a 74HC138. This IC has 3 input lines and 8 outputs. The input lines are used to control which of the 8 output lines that will be pulled low at any time. The rest will be high. Each out the outputs on the 74HC138 is connected to the CP pin on one of the latches.
The following pseudo-code will load the contents of a buffer array onto the latch array:
// PORT A = data bus
// PORT B = address bus (74HC138)
// char buffer[8] holds 64 bits of data for the latch array
PORTB = 0x00; // This pulls CP on latch 1 low.
for (i=0; i < 8; i++)
{
PORTA = buffer[i];
PORTB = i+1;
}
The outputs of the 74HC138 are active LOW. That means that the output that is active is pulled LOW. The latch pin (CP) on the latch is a rising edge trigger, meaning that the data is latched when it changes from LOW to HIGH. To trigger the right latch, the 74HC138 needs to stay one step ahead of the counter i. If it had been an active HIGH chip, we could write PORTB = i; You are probably thinking, what happens when the counter reaches 7, that would mean that the output on PORTB is 8 (1000 binary)on the last iteration of the for() loop. Only the first 8 bits of PORT B are connected to the 74HC138. So when port B outputs 8 or 1000 in binary, the 74HC138 reads 000 in binary, thus completing its cycle. (it started at 0). The 74HC138 now outputs the following sequence: 1 2 3 4 5 6 7 0, thus giving a change from LOW to HIGH for the current latch according to counter i.
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pls help my Email:
ehsan.eas.ahmadi@gmail.com
i will apreciate any kind of help.
my email is alexandre-alex@ig.com.br
Thks in advance !
Or am I reading the schematic wrong to begin with? Is that dark blue line just a convention that means that all LIKE pins are connected connected, such as all D1s are connected to all other D1s, all D2s are connected to all other D2s, etc., or are all those pins (D1s, D2s, D3s, D4s, etc.) REALLY on a single, common bus? Any help would be appreciated.
They are actually all different cables.. imagine a cat5 network cable, it has 8 wires inside it, but its all just 1 cable.
Although it can be confusing, these data buses normally have labels to show what each wire is.
Im going on the assumption that D0 is connected to 1D pins on all the multiplexers, D1 to 2D pins, D2 to 3D pins.. etc.
So a high on D1 will be a high on all 1D pins.
Then the data is latched into a specific 574 by toggling the clock pin of that specific chip via the 138
I hope i make sense..
does this mean to connect all the 1D pins of all the latches to the D0 pin of the ATmega.......??
All the data pins of the 574's are connected together.
1D to all other 1D's, 2D to all other 2D's.. etc.
This way, you only need 8 pins on the microcontroller to send data to all chips at the same time. But only the chip with OC low will actually read the data on the rising edge of the clock signal and set its pins accordingly to that when OC goes high.
Its been a while since i've used the 74HC574N, but at least the theory of it is sound.
does this mean to connect all the 1D pins of all the latches to the D0 pin of the ATmega.......??
How is the 74HC574 supposed to be programmed?
Can someone please explain me?
I am confused but i would really like to make this cube, can someone explain me how the 74HC574 should be programmed, or if I am completely wrong, can someone point me in the right direction?
Thanks
I do consider myself a beginner but I really want to finish this cube.
Once again thank you
You can just change the file from *********.tmp to **********.sch and open it in EAGLE CAD. :-)
I am looking for the schematic files. Did someone managed to download them and construct the cube?
I am newbie, whenever i click on the attached file (multiplex_theoretical.sch), it is downloaded as .tmp file further more i dnt have eagle also can anyone send me link of that software !
Regards !
Did you manage to download the file?
John
Think you!!!
my e-mail :461421228!qq.com or yww336600@163.com
I hope to make it usb compatable and yet still beeing able to run without a computer
it´s still the same but uses the shiftregister 74HC164
would it work with the software?