Bio Impedance Analysis (BIA) With the AD5933

I have been interested in making a Bio Impedance Analyser for body composition measurements and my random searches kept finding a design from the 2015 Biomedical Instrumentation class at Vanderbilt University. I have worked through the design and improved it slightly. I would like to share my findings with you. Take what you can use from this "walk-through" if something isn't clear please suggest improvements. I might someday write my thought up in a more cohesive form, but for now I hope you can use whatever you see here. (If you think you can write this up and improve, you are welcome)

Teddy

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This design consists of the AD5933 chip and a custom analog front-end (AFE) to interface the AD5933 with the body. The AD5933 then does the measuring and the results can then be processed by a microcontroller (e.g. an Arduino).

If you plan on using the Arduino as a power supply make sure that the operational and instrumentation amplifiers (op-amps and in-amps) support so-called "single supply" voltages and have rail-to-rail specs.

(In the following I will be using a power supply (from an Arduino) of 5V and the Range 1 setting on the AD5933.)

Step 1: The Re-bias Stage

The first part of the AFE is a re-bias stage. The output voltage signal is not centered in the middle of the supply voltage range (VDD/2). This is corrected by using a capacitor to block the DC part of the signal and sending it through a voltage splitter to add a DC offset back into the signal.

The two re-bias resistors can be any value as long as they are the same. The specific value af the cap is also not important.

The re-bias stage works like a high pass filter and therefore has a cutoff frequency:

f_c = 1 / (2*pi * (0.5*R) * C)

Make sure that the cutoff frequency is a few decades below the minimum frequency you plan on using. If you plan on using 1kHz in your application you should go for caps and resistor values that will give you a cutoff frequency on the order of 1-10 Hz.

The last part of this stage is an op-amp set up to be a voltage follower. This is to make sure that the resistor values do not interfere with the next stage

Step 2: Current Sensing Resistor

The first part of the next stage is the current sensing resistor. The current through this resistor will be the same current that the amplifier will try to maintain through the body. Make sure that the current complies with the IEC6060-1 safety standards* :

Below frequencies of 1 kHz a maximum of 10 microAmps(RMS) are allowed through the body. At frequencies above 1kHz the following equation gives the maximum allowed current:

Max AC current < (minimum frequency in kHz) * 10 microAmps(RMS)

The relation between the peak amplitude of an AC signal and its RMS value is: Peak = sqrt(2) * RMS. (10 microAmps RMS correspond to 14 microAmps peak amplitude)

Using Ohms Law on the resistor we can calculate the resistor value that will comply with the safety standard. We use the excitation voltage from the AD5933 and the max current value:

U = R * I => R = U / I

E.g. using the Range 1 setting Upeak = 3V / 2 = 1.5V (or 1V @3.3V)

Using the 14 microAmp peak value from above I get a resistor value of at least 107kOhms

References:

* Analog Devices: "Bio-Impedance Circuit Design for Body Worn Systems"

Step 3: The Trans-conductance Amplifier

After the current sensing resister there is an op-amp in a negative feedback configuration. This is a so-called Load-in-the-Loop setup. The positive input terminal of the op-amp is connected to a VDD/2 voltage. The op-amp will now try to adjust its output in the opposite direction to the excitation signal such that the voltage at the negative terminal will be equal to VDD/2. This will produce a seesawing potential pushing and pulling the current through the body.

The current drawn from the negative terminal of the op-amp is virtually zero. All the current through the current sensing resistor therefore has to flow through the body. This is the mechanism that makes this setup a trans-conductance amplifier (also called a voltage controlled current source, VCCS).

The op-amp can only maintain the current if the impedance of the body is not too high. Otherwise the op-amp output would just max out at the supply voltage (0 or 5 V). The maximum voltage span that can be maintain is VDD/2 + Upeak (2.5+1.5V = 4V @ 5V supply). The voltage margins of the op-amp should be subtracted from this value, but if the op-amp has rail-to-rail specs that would only be a small amount. The maximum impedance that the op-amp can drive is therefore:

Z < (VDD/2 + Upeak) / Imax

(In my setup Z < 4V / 14 microAmps = 285 kOhms, wish is plenty to cover the impedance range of the body)

The protector resistor has a very large value (1-1.5 MOhms) compared to the body (approx 100kOhms) and for all normal operations this will not draw any noticeable current and the impedance of the parallel connection is dominated by the impedance of the body. If the impedance of the body should rise (e.g. pads coming loose) the current can then go through the resistor and the maxing out of the op-amp would not create unpleasant voltages in the pads.

Step 4: The Instrumentation Amplifier

The next stage is the instrumentation amplifier (in-amp) which measures the voltage across the body. The voltage across the body is oscillating around 0V, but the AD5933 needs the input voltage to be in a positive range. The in-amp therefore adds a DC offset of VDD/2 to the measured voltage signal.

The VDD/2 reference is generated by a voltage divider. Any value resistor can be used as long as they are the same. The voltage divider is separated from the impedance of the rest of the circuitry by a voltage follower. The output of the voltage follower can then be forwarded to both the in-amp and the trans-conductance amplifier.

Step 5: The Input Stage and Calibration

The input stage of the AD5933 contains an op-amp in negative feedback configuration. There are two resistors: one in series (Rin) and one in parallel (RFB). The gain of the op-amp is given by

A = - RFB / Rin

The gains of the input op-amp and the in-amp (and PGA) need to make sure that the signal going into the ADC of the AD5933 is always within 0V and VDD.

(I use a unity gain in-amp and resistor values that will give approx A = 0.5)

Inside the AD5933 the ADC will convert the voltage signal into a into a digital signal. The voltage range from 0V to VDD is converted to the digital range 0-128 (2^7). (The documentation is not clear on this but a close examination of the plots in [1] and som experimentation on my part confirms this.)

Inside the DFT module there is another scaling of 256 (1024/4, see [1]) before the result is saved in the real and imaginary register.

By following the voltage signal trough the AFE, into the ADC and using the scale factors mentioned before it is possible to estimate the gain-factor to be:

g = (VDD * Rcurrent * Rin) / (256 * PGA * Upeak * RFB * 2^7)

some calibration might still be necessary so account for some effects not part of this mathematical model, so please measure the true gain value by measuring components of known impedance, like resistors. (g = Z / mag, see below)

The impedance can now be calculated by

Z = g * mag

mag = sqrt(real^2 + imaginary^2)

PA = arctan2(real,imaginary) - deltaPA

The PA probably needs to be calibrated as well as there is a systematic phase-shift as a function of frequency in the AD5933. deltaPA will probably be some linear function of frequency.

The resistance and reactance can now be calculated by

R = Z * cos(PA)

X = Z * sin(PA)

References:
[1] Leonid Matsiev, "Improving Performance and Versatility of Systems Based on Single-Frequency DFT Detectors Such as AD5933", Electronics 2015, 4, 1-34; doi:10.3390/electronics4010001

Step 6: Advanced Stuff: Spectral Leakage (DC)

The signal that we put into the AD5933 is a voltage/current as a funktion of time, but our main interest is the impedance as a funktion of frequency. To convert between time-domain and frequency-domain we need to take the Fourier transform of the time-domain signal. The AD5933 has a build-in discrete Fourier transform (DFT) module. At low frequencies (below approx 10 kHz) the build in DFT is influenced by aliasing and spectral leakages. In [1] he go through the mathematics of how to correct the spectral leakage. The essence of this is to calculate five (plus two) constants for each frequency step in the sweep. This can easily be done e.g. by the Arduino in software.

The leakage comes in two forme: a DC leakage which is additive in nature and an AC leakage which is multiplicative in nature.

The DC leakage stems from the fact that the voltage signal at the ADC is not oscillating around 0V but around VDD/2. A DC level of VDD/2 should corresponds to a digital DC reading of approx 64 (designated delta in [1]).

The steps to correct the DC spectral leakage:

1) Calculate the Envelope-factor E for the current frequency.

2) Calculate the two gain factors GI (real) and GQ (imaginary)

3) Subtract delta * GI from the value of the real register and delta * GQ from the value of the imaginary register

References:

[1] Leonid Matsiev, "Improving Performance and Versatility of Systems Based on

Single-Frequency DFT Detectors Such as AD5933", Electronics 2015, 4, 1-34; doi:10.3390/electronics4010001

[2] Konrad Chabowski, Tomasz Piasecki, Andrzej Dzierka, Karol Nitsch, "Simple Wide Frequency Range Impedance Meter Based on AD5933 Integrated Circuit", Metrol. Meas. Syst., Vol. XXII (2015), No. 1, pp. 13–24.

Step 7: Advanced Stuff: Spectral Leakage (AC)

Like the DC leakage the AC leakage can be corrected mathematically. In [1] the resistance and reactance are called A*cos(phi) and A*sin(phi) respectively, where A corresponds to the magnitude of the impedance and phi corresponds to the phase angle (PA).

The steps to correct the AC spectral leakage:

1) Calculate the Envelope-factor E (not he same as for DC) for the current frequency.

2) Calculate the three factors a, b, and d. (approx values at higher frequencies: a = d = 256 and b = 0)

3) Resistance (Acos(phi)) and reactance (Asin(phi)) can now be calculated in digital units

References:
[1] Leonid Matsiev, "Improving Performance and Versatility of Systems Based on Single-Frequency DFT Detectors Such as AD5933", Electronics 2015, 4, 1-34; doi:10.3390/electronics4010001

Step 8: Advanced Stuff: the Theoretical Gain-factor

Given the mathematical modeling of the DFT it should also be possible to model the whole AFE mathematically. Mathematically the voltage signal can be described by a sine function with a given fixed frequency, a DC offset and an AC oscillation with a peak amplitude. The frequency does not change during a frequency step. As the gain-factor only changes the magnitude of the impedance and not the PA we will here not be concerned with any phase shift induced on the signal.

Here is a short summary of the voltage signal as it propagates through the AFE:

1) After the re-bias stage the AC amplitude is still Upeak=1.5V (1V @ VDD=3.3V) and the DC offcet has been changed to VDD/2.

2) In the current sensing resistor the voltage is stille the same as the previous stage ...

3) ... but due to the seesaw-voltage of the op-amp the AC oscillations have a size of Z*Upeak/Rcurrent. (The DC offset is canceled out by the op-amps reference voltage of VDD/2 - the pivot point of the seesaw - and becomes a virtuel ground in this part of the circuit)

4) The unity in-amp adds the DC offset of VDD/2 back in and forwardes the signal to the input stage of the AD5933

5) The op-amp in the input stage has a gain of A=-RFB/Rin and the AC amplitude therefore becomes (Z*Upeak/Rcurrent)*(RFB/Rin)

6) Just before the ADC there is a programmable gain amplifier (PGA) with two settings a gain of 1 or 5. The voltage signal at the ADC therefore becomes: PGA*(Z*Upeak/Rcurrent)*(RFB/Rin)

The ADC converts the v(t) signal into a digital signal x(t) = u(t) / VDD * 2^7 with a 12 bit accuracy.

The magnitude A is connected to the impedance Z by the gain factor, k, as A = k * Z and has an approx value of k = PGA * Upeak * RFB * 2^7 / (VDD * Rcurrent * Rin).

The if you like to work with gain-faktor instead g = 1 / k and Z = g * A.

Equations.docx
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Step 9: Advanced Stuff: the PA Shift

In [2] they find a systematic shift in the PA as a function of frequency. This is due to a time delay between the DAC where the excitation signal is generated and the DFT where the incomming signal needs to be convoluted with the outgoing signal.

The shift is characterized by the number of clock-cycles the signal is delay between the DAC and DFT internally in the AD5933.

References:
[1] Leonid Matsiev, "Improving Performance and Versatility of Systems Based on Single-Frequency DFT Detectors Such as AD5933", Electronics 2015, 4, 1-34; doi:10.3390/electronics4010001