Introduction: Creating Custom Vivado IP
Sometimes it may be necessary to use custom HDL code with a MicroBlaze Design. For example, I have working HDL for controlling a stepper motor using the PmodSTEP and wanted to create a MicroBlaze design to control the motor.
Luckily Vivado has a utility that allows this functionality. I will be creating a IP for the PmodSTEP as an example but any Verilog or VHDL design can be made into IP with this method.
- Verilog or VHDL project to be made into IP
Step 1: Open the IP Packager
With the Vivado project open, got to Tools->Create and Package IP.... This will open a dialog for preparing the project for IP packaging. I will step through and describe the options in the next few steps. Click Next on the first section for now.
Step 2: Choose the IP Type
This gives several options for the kind of IP peripheral to create. For this tutorial I will go through the first option for packaging the current project. This option will use the currently open project as the source for the IP.
The other options allow for packaging a block design, selecting a directory with the sources, and creating a new AXI4 peripheral.
Step 3: Finish With the Wizard
The next screen asks where you would like to keep the IP definition and any other files needed for saving options. Normally you would point this at a general location for all custom IP. For simplicity I'm going to leave it in the project directory. Select Include .xci Files and click Next. This is the end of the wizard so click Finish to save and exit.
Step 4: Review and Package IP
The IP packager allows for a lot of customization, but for this tutorial we won't do any customization so go to the Review and Package pane to check the settings before packaging the IP. Once you are satisfied with the settings click the button at the bottom of the pane to Package IP.
Step 5: Add the IP to a Block Design
Now that the IP block has been packaged open another project and add the Project Directory as an IP Repository for the project you want to add the block to. The block can now be added to the block design like any other IP.
Participated in the