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In this instructable, Designing a simple I2C master in VHDL is discussed.

NOTE: click on each image to see full image.

Step 1: I2C Bus Overview

•Stands for Inter Integrated Circuit.

•Synchronous , Half duplex.

•Two Wire Interface - SDA and SCL.

•SDA – Serial Data line controlled by Master and Slave

•SCL – Serial Clock generated by Master

•Multi-master , Multi-slave protocol.

•Two modes - 100 kbits/sec and 400 kbits/sec : slow and fast.

Step 2: RTL Design in VHDL

Design Specs of our I2C Master

8-bit data frame.
SCL uni-directional control only.
7-bit slave address.
Supports both slow and fast modes.
Single Master, Multi-slave.
Complied with original I2C specs by Philips.

Pure RTL code is used. So the IP is easily portable across all FPGAs. Compact FSM based design using internally generated clock ensures optimal area and performance.

Step 3: Simulation and Testing

Test Environment

Functional simulation and testing using third-party I2C Slave IP.
Synthesised using Xilinx Vivado tool set.
Implemented and tested on Artix-7 FPGA board.
Timing verified design for 100 MHz.
Tested waveforms on DSO/CRO.
Successfully tested communication with Arduino UNO as I2C Slave.

Step 4: Important Notes

While testing Master using I2C Slave IP, configure the slave code as per your requirements. You may want to change the default clock frequency and slave address. Clock frequency should be configured in the Master code too.
While on-board testing, don't forget pull-up resistors as SDA line is common drain output !!! Check google for recommended pull-up resistor for different i2c speeds. I used 2.2K for 100 kHz.
If not using test bench and simulating the Master independently, carefully simulate SDA signal, as it is a bi-directional signal (inout) signal. It has two drivers, master side and slave side. You should know when to 'force' and when to 'unforce'.
SCL is unidirectional line. No need of pull-up.
Please go thru the IP Documentation thoroughly.