Introduction: Design of SPI Master in VHDL

About: Mitu Raj -- Just a Hobbyst and Learner -- Chip Designer -- Software Developer -- Physics and Mathematics Enthusiast

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In this instructable, we are going to design an SPI Bus Master from scratch in VHDL.

Step 1: Overview of SPI

  • SPI is a synchronous serial bus
  • Its popularity and simplicity made it a de facto standard in serial communication
  • Full-duplex bus
  • Simple protocol and among the fastest serial bus

Step 2: Design Specifications

These are the specifications of the SPI Master we are gonna design:

  • Supports all four modes of operation; dynamically configurable
  • Clock enable control for power saving
  • Statically configurable word length and speed
  • Single interrupt for both transmission and reception

Step 3: Starting Off

First of all, our IP should have two interfaces. One is serial interface and the other is parallel interface. Serial interface consists of the de-facto standard signals of SPI : MOSI, MISO, SS, SCLK.

MOSI is sometimes called SDO and MISO is sometimes called SDI.

Serial interface is used to communicate with external peripherals ie., SPI slaves.

Parallel interface is used to communicate with our host ie., a microcontroller or microprocessor, which actually tells the Master what data has to be serially transmitted and received thru the serial lines. ie., All data buses belong to parallel interface.

We have a global clock that drives internal SPI logic, as well as SCLK, which we generate internally.

We also have some control signals like write enable, clock enable. And interrupt and other status signals.

Since we have to deal with complex control conditions, it is simpler to design such serial communication IPs as an FSM. We will design SPI master as an FSM as well. The FSM will be driven by another internal clock which is two times SCLK. That internal clock is generated using synchronous counters from the global clock.

All control signals that cross clock domains have synchronisers to be on the safer side.

Step 4: RTL View of the SPI Master Core and Simulation Waveforms

It is a bare RTL design with no dedicated FPGA IPs used. Hence it is a fully portable code to any FPGA.

Check out the RTL View of the IP core ( click to see full image).

Check out the simulation waveforms as well.

Step 5: Test Environment

  • Tested on Basys-3 Artix-7 FPGA
  • Timing verified design up to 200 MHz main clock, 50 MHz SCLK
  • Tested SPI Master @Clock speed 1 MHz with Arduino UNO as slave
  • Tested waveforms in DSO as well

Step 6: Files and Important Notes

  • Find the IP in the attached RAR file.
  • Please go through the IP documentation and readme that comes along with the RAR file.
  • Find all source files in the RAR: main codes, test benches
  • Synthesisable testbench is provided with the IP, which you can synthesise and test on any FPGA board at any desired configuration.

SPI Master v.1.0 is an FPGA proven IP with free open source license.

For queries regarding on-board testing, timing verification and driver writing, contact anytime:

Mitu Raj