Introduction: FPGA Based Heart Diseases Detector


This tutorial shows a way of designing a Heart Diseases Detector using Nexys Video board.

This project combines electronics and medicine in order to obtain a product that detects hearth diseases.

The results of this project don't compare with an examination and therefore the resuls cannot be considered valid - this is a project made for a contest and not for medical purposes.

The aim of the project is to compare signals from MIT-BIT database with the signals acquired from the patients and returns a response to the tested person.

Step 1: Dowload the Patterns

The patterns are Matlab files which include 3 types of files: .atr, .dat, .hea. After you've downloaded the files, you need to add their name in the code. The code will be atached down here :-) .On the first part, you need to add the path and the files for every signal. Remember that MIT-BIH data base has sampling frequency = 360 Hz, so you need to obtain this frequency from FPGA. On the specific data, you also have a variable called SAMPLES2READ which shows the number of periods to be displayed.

The files for database must be downloaded from here: MIT-BIT data base.

Step 2: Blocks(ADC and RAM)

The TOP module consist of 4 important blocks:

  • ADC
  • RAM
  • RX
  • TX

It is necessary to reduce the standard frequency of 100 MHz to 360 Hz, due to the sampling frequency of the MIT-BIH database; that's why the ADC block has multiple components: PLL, XADC, Frequency Divider.

The RAM :

  • 2048 memory locations
  • one memory location = 12b

Because the control for writing and reading from the memory needs to be easily done, this block is controlled from an input port : we (write enable).

When the memory is full, a pulse is generated on the pin pulseMem to inform the transmission block to start the transfer to the PC.

Step 3: Transmission

The transmission block waits for the memory to be full and after that it sends information to the PC. Because our signal has 12b - we chose to transmit 2 packages of 8 bits:

  • the first package [b7 b6 b5 b4 b3 b2 b1 b0]
  • the second package [0 0 0 0 b11 b10 b9 b8]

The state machine has a counter for transmissions and only if this counter is even, and the program goes to the next address.

In this case it is needed an PC application which knows to wait the second package before plotting the signal.

Step 4: Codes