Introduction: How to Make 8-bit SISO, SIPO, PISO, PIPO Shift Registers

By Renesas
About: GreenPAK™ is a broad family of cost-effective NVM programmable devices that enable innovators to integrate many system functions into a single custom circuit.

Registers are sequential circuits made with flipflops to store and transfer binary information. Shift registers are primarily made with D flipflops in a daisy chain structure. These flipflops can each store one bit of binary information, all of which are controlled by a shared input clock. DFF's can read and store the value of the input signal at every rising edge of the clock. This property of the DFF can be used to build various registers. Different forms of registers like SISO, SIPO, PISO, PIPO are differentiated by the way data is loaded and retrieved.

The implementation illustrated in this Instructable consists of 8-bit shift registers which are designed with GreenPAK™ SLG46533 IC. The number of bits in a shift register corresponds to the number of flipflops present; in this design eight DFFs are used.

Below we described steps needed to understand how the solution has been programmed to create 8-bit SISO, SIPO, PISO, PIPO shift registers. However, if you just want to get the result of programming, download GreenPAK software to view the already completed GreenPAK Design File. Plug the GreenPAK Development Kit to your computer and hit the program to design the devices.

Step 1: SISO Shift Register

SISO is one of the most basic forms of the shift registers. The data is loaded serially and retrieved serially. The output of the first DFF is fed into the input of the next DFF at each clock cycle, eventually reaching the last DFF / Output. This Shift register output is delayed from the input. The shift register shifts, or streams, one-bit data per clock cycle.

As shown in the design in Figure 1, DFF3 is fed with the input data bits serially and the output is taken from DFF10 serially. All the DFFs share the same clock. nReset is set high to ensure that all DFF's are enabled for normal operation.

The timing diagram shown in Figure 2 has clock and input data stream as first and second waveforms. The rest of the waveforms show how the output of each DFF shifts serially. If we consider the first 8 input bits which are 10011010, we can clearly observe that these 8 bits appear one after another by the 8th rising edge clock at the output of DFF10.

One of the main applications of the SISO register is to act as a delay element. The delay can be controlled by the number of stages in the register and the frequency of the clock. In the design in Figure 2 the clock is at 1kHz, so the delay that is observed is 7 ms.

Step 2: SIPO Shift Register

In this type of shift register, the data is sent serially and retrieved in parallel. All the DFF's are clocked by the same clock and nReset is used to ensure that all the DFF's are enabled for normal operation. The data is fed serially into DFF3. All the parallel outputs are from the outputs of the DFF that are present in the shift register. The output of each intermediate DFF is fed as input to the next DFF. All 8 input serial bits will be available at the parallel outputs after 8 rising edges of the clock.

The timing diagram of the SIPO shift register is shown in Figure 4. It has a clock and Serial Data-in as the first two waveforms, and all other waveforms are the outputs of the DFF's. It can be observed that after the 8th rising edge of the clock, the entire input data bits are visible at the output of each DFF.

The first bit which is transmitted serially is observed at the last DFF's output. The main application of the SIPO shift register is data conversion in many digital applications. Sometimes the SIPO shift register is connected to the output of a microprocessor when more GPIO pins are required. In the design in Figure 3, the clock frequency is 1 kHz and the time taken to convert the 8 serial bits to parallel bits is 8 ms.

The correspondence between input to output is shown in Figure 4.

Step 3: PISO Shift Register

The PISO shift register is the converse of the SIPO shift register. The inputs are presented simultaneously in parallel, and the output is retrieved serially. The data is taken out one bit per clock cycle. The main point to note in this shift register is that a clock is not required to load the data in the shift register, whereas a clock is required to unload the data.

Similar to the other shift registers, all the DFF's are clocked by the same clock and have the nReset set high for normal operation. 2-bit lookup tables provided in the IC are used as OR gates to provide parallel input to the DFF's as well as transmit the output of one DFF as the input to the next DFF. The output is retrieved serially from the output of DFF10.

This type of shift register is typically used for data conversion from parallel to serial. All the parallel bits with the data are serially transmitted to the single input of a microprocessor which helps in using fewer input pins of the microprocessor.

The timing diagram shown in Figure 6 depicts the clock and all parallel inputs, highlighted between two vertical orange lines. The last waveform is the serial data out which shows how all the parallel inputs are converted into a serial bitstream.

The way how inputs correspond to output is shown in Figure 6.

Step 4: PIPO Shift Register

This shift register is the converse of the SISO shift register. The input data is given and retrieved in parallel. The output changes with respect to the input within the same clock cycle. Similar to the PISO shift register, a clock is not required to load data into the flipflops, but to latch and transfer out. Hence a PIPO shift register can be used as a temporary storage device, though in practice other GreenPAK capabilities are often included within the design. Whenever new data output is required, a rising edge clock presents the DFF content to the output. One note about this shift register is that there is no connection between individual DFFs. Similar to other shift registers, the same clock and nReset are applied to all the DFF's.

The timing diagram of the PIPO shift register is shown in Fig. 8. As all the inputs and outputs are loaded and unloaded separately, it results in a large number of waveforms to show. The yellow highlighted line in the waveforms separates the input and the output. All the top waveforms are inputs and the bottom waveforms are outputs. It's clearly visible from the waveforms that the loaded data can be retrieved with a single clock pulse.

Cost Comparison

The GreenPAK SLG46533 IC is a very versatile CMIC. Many applications have been implemented with this IC. Table 1 (all the prices of the ICs are referred from Digi-Key on 08-05-2020) shows some of the competing IC's that are available in the market for shift register applications.

GreenPAK SLG46533 IC is of size 2.00 mm x 3.00 mm and costs less than $ 0.50. It is clearly visible that the GreenPAK IC is one of the best solutions that are available in the market. Moreover, the user has control over the configuration of the IC in GreenPAK, which increases its value.

Conclusions

Shift registers are an integral part of any digital system. In this Instructable, four types of shift registers, SISO, SIPO, PISO, PIPO have been configured within the GreenPAK SLG46533 IC. The 8-bit shift registers in this Instructable form a viable alternative to other shift registers available on the market. The GreenPAK SLG46533 IC has the advantage of a low PCB area footprint, more circuitry available, and lower cost.