Introduction: Interfacing the AXI TFT Controller With the MIG IP and Using It to Display Using the VGA Port on the Nexys4 DDR Board

This tutorial is the third part of a three part series that deals with setting up the MIG IP provided by Xilinx to use the DDR memory on board the Nexys4 Board and interfacing it with the AXI TFT IP to use the VGA port on the board.

Please make sure you have configured the MIG for use with the board that you are using. If you haven't, please follow the first tutorial and configure the DDR2 memory on the Nexys4 and then configure the MIG IP using the second tutorial before proceeding further.

Once, you have the MIG set up, you need to instantiate an AXI TFT Controller IP.

The way the AXI TFT functions is that it needs a memory device as its slave and this memory is where it stores the frame buffer for display.

For more information on the AXI TFT please refer Xilinx's AXI TFT user manual or use the comments section below.

Step 1: Double Click the AXI TFT Controller IP and Make Sure the Following Changes Have Been Made:

TFT Interface: VGA

AXI Data Width: 32

Maximum Burst Length: 256

Step 2: Run Connection Automation As Follows:

a. Connect /axi_tft_0/M_AXI_MM to /mig_7series_0/S_AXI

b. Connect /axi_tft_0/S_AXI_MM to microblaze_0

Step 3: Connect the TFT Sys_tft_clk to Clk_out3 (25 MHz). Make Tft_vga_r, Tft_vga_g, Tft_vga_b, Tft_vsync, Tft_hsync External Ports.

The .xdc file contains the pin constraints for the external ports for the VGA. Add these to the constraints file. Ensure the ports in this file match the ports in your external design.

Step 4: Generate the Block Design.

Step 5: ​Before Running Synthesis, Some Modifications Are Necessary. Please Read the Following Steps:

The TFT outputs in RGB666 format. The Nexys4DDR board only has pins for RGB444. So the two LSBs of each colour’s external port need to be truncated. Open the top-level HDL wrapper and make this change. The design_1(top-level)/tft_vga_r port is of size 6 bits. The design_1_wrapper(wrapper)/tft_vga_r port is also of size 6 bits, but should be changed to 4 bits, and assigned to the 4 most-significant bits of design_1(top-level)/tft_vga_r. Do the same for green and blue ports. If this change is not made, it will cause a bitstream generation error as some external ports will not be assigned to pins.