Introduction: Introduction to IC555

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The IC was designed in 1971 by Hans R. Camenzind under contract to Signetics (later acquired by Philips Semiconductors, and now NXP)

It has been falsely hypothesized that the 555 got its name from the three 5 kΩ resistors used within, but Hans Camenzind has stated that the part number was arbitrary, thus it's just a coincidence they matched. The "NE" and "SE" letters of the original parts numbers (NE555 and SE555) were temperature designations for analog chips from Signetics, where "NE" was commercial temperature family and "SE" was military temperature family.

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network.

Step 1: Features & Pin Description


• Timing From Microseconds to Hours

• Astable or Monostable Operation

• Adjustable Duty Cycle

• TTL-Compatible Output Can Sink or Source Up to 200 mA

Pin Description

Pin 1 GROUND: Connects to the 0v rail.
Pin 2 TRIGGER: Detects 1/3 of rail voltage to make output HIGH. Pin 2 has control over pin 6. If pin 2 is LOW, and pin 6 LOW, output goes and stays HIGH. If pin 6 HIGH, and pin 2 goes LOW, output goes LOW while pin 2 LOW. This pin has a very high impedance (about 10M) and will trigger with about 1uA.

Pin 3 OUTPUT: (Pins 3 and 7 are "in phase.") Goes HIGH (about 2v less than rail) and LOW (about 0.5v above 0v rail) and will deliver up to 200mA.

Pin 4 RESET: Maybe internally connected HIGH via 100k in some chips, but NOT others!!. Must be taken below 0.8v to reset the chip.

Pin 5 CONTROL: A voltage applied to this pin will vary the timing of the RC network (quite considerably).

Pin 6 THRESHOLD: Detects 2/3 of rail voltage to make output LOW only if pin 2 is HIGH. This pin has a very high impedance (about 10M) and will trigger with about 1uA.

Pin 7 DISCHARGE: Goes LOW when pin 6 detects 2/3 rail voltage but pin 2 must be HIGH. If pin 2 is HIGH, pin 6 can be HIGH or LOW and pin 7 remains LOW. Goes OPEN (HIGH) and stays HIGH when pin 2 detects 1/3 rail voltage (even as a LOW pulse) when pin 6 is LOW. (Pins 7 and 3 are "in phase.") Pin 7 is equal to pin 3 but pin 7 does not go high - it goes OPEN. But it goes LOW and will sink about 200mA. You can connect pin 7 to pin 3 to get a slightly better SINK capability from the chip.

Pin 8 SUPPLY: Connects to the positive rail

Step 2: Mode of Operation

The IC 555 has three operating modes:

  • Astable
  • Monostable
  • Bistable

Astable Mode: In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a specified frequency. The 555 Circuit for astable mode is given in fig.

Input and Output Wave form of circuit.

Note: this waveform is plotted using Circuit wizard. Red color shows Output wave while blue color shows Input waveform

Formules to calculate timing:

1) TH = 0.693(R1+VR1)C1

2) TL = 0.693(VR1)C1

3) Period = TH+TL

4) Frequency = 1.44/((R1+2VR1)C1)

Monostable Mode: In monostable mode, the output pulse ends when the voltage on the capacitor equals  2⁄3 of the supply voltage. The output pulse width can be lengthened or shortened to the need of the specific application by adjusting the values of R and C.


t= 1.1RC

Bistable Mode: In bistable mode, the 555 timer acts as a basic flip-flop. The trigger and reset inputs (pins 2 and 4 respectively on a 555) are held high via pull-up resistors while the threshold input (pin 6) is simply floating. Thus configured, pulling the trigger momentarily to ground acts as a 'set' and transitions the output pin (pin 3) to VCC (high state). Pulling the reset input to ground acts as a 'reset' and transitions the output pin to ground (low state). No timing capacitors are required in a bistable configuration. Pin 7 (discharge) is left unconnected, or may be used as an open-collector output.

A 555 timer can be used to create a schmitt trigger which converts a noisy input into a clean digital output. The input signal should be connected through a series capacitor which then connects to the trigger and threshold pins. A resistor divider, from VCC to GND, is connected to the previous tied pins. The reset pin is tied to VCC.

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