JDM Programmer Review

Introduction: JDM Programmer Review

About: I like to share good ideas.

JDM is a popular PIC programmer because it uses a serial port, a bare minimum of components and requires no power supply. But there is confusion out there, with many programmer variations on the net, which ones work with which PICs ? In this “instructable” we put JDM to the test and I demonstrate how to simulate the circuit using Spice which will answer all of your questions !

Supplies

LTspice which can be downloaded from Analog Devices here.

You also need the JDM circuit files here.

Step 1: Serial Port Requirements

JDM requires a serial port meeting EIA232 specification, ideally with +12/-12 Voltage levels.

According to Texas Instruments Line Driver MC1488 datasheet (Figure 3)

Output impedance = 4V/8mA = 500 ohm.

Short circuit current limit =12mV, with no time limit - no damage to chip.

Input impedance of line receiver = 3k to 7k ohm recommended.

Serial ports on older desktop PCs use +12v/-12V meeting this requirement.

Serial ports on newer laptop PCs use lower voltages. JDM may or may not work - the answer is more complex.

Step 2: PIC Programming Requirements

Information concerning PIC programming requirements is obtained from Microchip. The above is for a typical device.

Step 3: JDM Specification

Has the original JDM web site been lost in the mists of time? This leaves us guessing what the designer originally intended for the specification.

  1. Provide VDD=5V , and up to IDD=2mA maximum (for “in socket” version)

  2. Provide VHH=13V, and up to IHH=0.2mA maximum.

  3. MCLR Rise time tVHHR = 1uS max.

  4. ICSP version must be able to pull MCLR low against 22k pull-up on target.

Step 4: Circuit Description

Figure JDM1 is based on the “standard” JDM circuit taken from PICPgm web site. This is the “PIC in Socket” programmer where PIC takes power from TX and RTS pins. The original diagram was difficult to understand so I have redrawn it using the normal convention of current flow from top to bottom. And I have added LED indicators “RESET”, “PROG” and “RTS” which are necessary during construction and testing. Hopefully these do not have any detrimental effect on behaviour.

The normal convention of circuit design is to common all grounds, but the key feature of JDM is that serial port ground (GND) is connected to VDD. This creates confusion as serial port signals are measured with respect to GND, PIC signals with respect to logic ground (VSS).

When TX goes high, Q1 behaves as two forward biased diodes. (Q1 collector is not reverse biased as with normal transistor operation). Q1 collector charges C2, which is is clamped at VDD+8V by Zener (D3). Q1 emitter delivers 13V to MCLR for Program/Verify Mode.

When TX goes low it, capacitor C3 is charged through D1 and VSS is clamped at VDD-5V by zener (D5). Also TX is clamped at (VSS-0.6) by D1. Q1 is off, C1 holds its charge for next programming pulse. MCLR is clamped at 0V by D2, so the PIC is now Reset.

When RTS is high, clock is transmit to PGC. D4 clamp PGC at VDD logic high. When RTS is low, capacitor C3 is charged through D6 and VSS is clamped at VDD-5V by zener (D5). D6 clamps PGC at VSS or logic 0.

During programming, data sent out on DTR is read on PGD, which the PIC configures as input. When DTR is high, Q2 acts as “emitter follower” and PGD voltage is about (VDD-0.6) or logic 1. When DTR is low, Q2 acts as a bad transistor (emitter and collector pins reversed). Q2 pulls PGD low, which is clamped by D7 at VSS or logic 0.

During verify the PIC configures PGD as an output for sending data to the serial port. DTR must be set high, and data is read on CTS. When PGD output is high, Q2 is off, CTS = DTR = +12V. When PGD output is low, Q2 is on. Q2 collector draws current (12V+5V)/(1k+1k5)=7mA from DTR, and pulls CTS low, to VSS.

Step 5: Prepare for Simulation

Download LT spice, save and open the circuit files (*.asc) provided here. To simulate the circuit, we must give it some inputs, then “trace” the outputs. V1,V2 V3 simulate the 12V serial port with output impedance R11,R12,R13.

  • V1 generates 2 Program Pulses on TX from 0.5ms to 4.5ms

  • V2 generates burst of data pulses on DTR from 1.5 to 4.5ms

  • V3 generates burst of clock pulses on RTS from 0.5 to 3.5ms

The components V4, X1, R15 and R16 are all part of the simulation.

  • V4 generates 2 pulses from 2.5 to 4.5ms for verify data.

  • Jumper X1 simulates OUTPUT on PGD.

  • R15, R16 simulate the “loading” of PIC on VDD and MCLR.

Step 6: Modifications for ICSP

Figure JDM3 shows the version for “in circuit” programming. Modifications from original are

  1. Replace ZIF socket with ICSP connector.

  2. The PIC is now powered by supply to target circuit (V5).

  3. Remove 5V zener (D5).

  4. The little 100pF capacitor (C4) is moved next to the PIC on the target circuit.

  5. LEDs take power from circuit board where possible.

  6. The MCLR pull-up resistor(R10) and diode(D10) are required on target circuit.

  7. WARNING. The target board must have a “floating” supply, ideally a battery.

  8. Do not connect target ground (VSS) to computer/PC ground by connecting any other computer ports at the same time as JDM.

After simulating JDM1, the problem of long charge time on C2 became apparent. Then after reading Fruttenboel it appears that C2 and Q1 were added as a modification to the original. I cannot think what C2 and Q1 are intended to do apart from create problems. So for JDM4, we revert to the older design on Fruttenboel which is simple and straightforward to understand. D1 and D3/LED2 clamp MCLR between VSS and VDD+8V. The value of R1 is reduced to 3k3, just sufficient to illuminate LED2 at 12V.

JDM4 is also designed to work with weaker serial ports. When TX goes high (+9V), TX current source = (9-8)/(1k +3k3) = 0.2ma, just enough to pull MCLR high although insufficient to illuminate LED2. When TX goes low (about -7V), TX current sink =( 9-7)/1k = 2mA. LED1 current = (7-2 for led)/(2k7) = 1.8mA. MCLR pull down current = 7-5.5/3k3 = 0.5mA.

This circuit has also been tested (JDM5 simulation ) to see what happens with serial ports +/-7V minimum, where there insufficient voltage to sustain VHH=13V. The purpose of C1 now becomes apparent, C1 creates a short +ve boost to MCLR, a 33us spike on the rising edge of TX, sufficiently long enough for the PIC to enter programming mode, perhaps ? But remove jumper X2 (disable LED1) as there is insufficient current to pull MCLR low and illuminate LED1 together. When TX goes low, TX current sink = (7V-5.5V)/(1k+3k3) = 0.3mA, just sufficient to pull MCLR low against the pull-up R10.

Step 7: Simulation Results

To view the graphic files, it is better to right-click the links below, then select "Open link in New Tab"

Simulation 1: trace of MCLR, VSS, and RTS for original JDM1. Immediately observation 1,2 and 3 are apparent.

Simulation 2: trace of MCLR and VSS, and RTS for modified JDM2, which fixes previous problems.

Simulation 3: trace of PGD, VSS and PGC for JDM2 sending data in program mode. Observation 4 at 3.5mS.

Simulation 4: trace of PGD, VSS and CTS for JDM2 in verify mode (jumper X1 inserted) . OK

Simulation 5: trace of MCLR, VSS, PGD and PGC for JDM3. ICSP using power from circuit solves many problems.

Simulation 6: trace of MCLR, VSS, PGD and PGC for JDM4 with +/-9V serial port. MCLR rises immediately, fully working.

Simulation 7: trace of MCLR, VSS, and TX for JDM5 with +/-7V serial port and jumper X2 removed. C1 creates a +ve boost (spike) on rising edge of MCLR, just about sufficient to push MCLR above TX to 13V.

Step 8: Conclusions

Spice is really good at revealing “hidden secrets” of circuit operation. Evidently the JDM circuit works and is compatible with many PIC chips, but the following observations reveal possible limitations/compatibility issues/faults ?

  1. Long rise time of MCLR while C2 charges to VPP on the first pulse of TX. Fails specification 3.

  2. The serial port charges C2 when TX goes high and RTS goes low. But RTS also has the job of charging C3. When both occur at the same time this creates more load on RTS, consequently C3 looses charge (VSS rises) at 2ms on simulation. Fails specification 1.

  3. C3 looses charge (VSS starts to rise) after clock pulses stop at 3.5ms.

  4. What is the purpose of C2, it is needed at all ?

Solutions

  1. Presumably PICPgm uses a software “work-round”. It must apply a long TX pulse to precharge to C2, then only enter programming mode after the second TX pulse? For simulation I reduced value of C2 to 1uF to gives a rise time of 1ms. Not an ideal solution.

  2. Split C2 and C3 so they charge independently. One small modification to JDM2, C2 is referenced to GND instead of VSS.

  3. Solved by JDM3. ICSP is much more reliable as PIC is powered by target circuit.

  4. JDM4 solves problem 1. This is a straightforward design eliminating C2 altogether.

Step 9: And Finally

The proof of the pudding is in the eating. This JDM works so carry on using it.

And my recommendations are:

  • use JDM2 for in socket programming and 12V serial ports,

  • use JDM4 for ICSP programmer and serial ports above +/-9V,

  • use JDM4 with jumper X2 removed for serial ports above +/-7V.

References:

Analog Devices LT spice

picpgm

Fruttenboel

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