Mojo FPGA Development Board Shield

Introduction: Mojo FPGA Development Board Shield

Connect your Mojo development board to external inputs with this shield.

What is the Mojo development board?

The Mojo development board is a development board based around the Xilinx spartan 3 FPGA. The board is made by Alchitry. FPGA's are very useful where multiple processes must be executed simultaneously.

What will you need?

Supplies

Mojo development board

Gerber file

8 x 15k ohm resistors (optional*)

4 x 470 ohm resistors

4 x 560 ohm resistors

4 x CC seven segment displays

4 x 3mm LEDs

4 x SPDT tactile switches

1 x 4 position surface mount DIP switch

2 x 25 by 2 or 4 x 25 headers

1x 2 by 5 pin box head

Soldering iron

Solder

Flux

*(if these resistors are omitted internal pullup/pulldown must be enabled for relevant pins)

Step 1: Upload Gerber to Pcb Manufacturer of Your Choice

For my boards I ordered from JLC PCB.

The only change I made was the colour which I wanted to match the black of the Mojo.

Step 2: Board Assembly

When soldering I always find it useful to solder the lowest parts first so starting with the resistors is a good idea.

R5, R6, R7, R8, R9, R10, R11 and R12 are 15k ohm resistors used to pull down the switches (if you are using internal pullup/pulldown ignore this).

R1, R2, R3, R4 are 560 ohm resistors which are responsible for limiting the current through the 7 segment display.

R13, R14, R15, R16 are 470 ohm resistors which are responsible for limiting the current through the 4 LED's.

Next solder the dip switch, tactile switches, LED's, seven segment displays and box header connector in that order.

Now place the 25 by 2 (or 2 25 by 1) into the mojo to align the pins. Align the shield with the pins and solder it in place.

Step 3: Software Setup

For software referring to the Alchitry website will let you know what you need to get started and install the Xilinx ISE. However changing the .ucf file so it knows what pins are connected to what is important to get your program running.

Here is the .ucf file I use with the shield:

CONFIG VCCAUX=3.3;

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;

NET "clk" LOC = P56 | IOSTANDARD = LVTTL;
NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL;

NET "cclk" LOC = P70 | IOSTANDARD = LVTTL;

NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL;
NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL;
NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL;
NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL;
NET "spi_channel<0>" LOC = P46 | IOSTANDARD = LVTTL;
NET "spi_channel<1>" LOC = P61 | IOSTANDARD = LVTTL;
NET "spi_channel<2>" LOC = P62 | IOSTANDARD = LVTTL;
NET "spi_channel<3>" LOC = P65 | IOSTANDARD = LVTTL;

NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL;
NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL;
NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL;

NET "Q[0]" LOC = P26 | IOSTANDARD = LVTTL;
NET "Q[1]" LOC = P23 | IOSTANDARD = LVTTL;
NET "Q[2]" LOC = P21 | IOSTANDARD = LVTTL;
NET "Q[3]" LOC = P16 | IOSTANDARD = LVTTL;


NET "S[0]" LOC = P7 | IOSTANDARD = LVTTL;
NET "S[1]" LOC = P9 | IOSTANDARD = LVTTL;
NET "S[2]" LOC = P11 | IOSTANDARD = LVTTL;
NET "S[3]" LOC = P14 | IOSTANDARD = LVTTL;

NET "pb[1]" LOC = P30 | IOSTANDARD = LVTTL;
NET "pb[2]" LOC = P27 | IOSTANDARD = LVTTL;
NET "pb[3]" LOC = P24 | IOSTANDARD = LVTTL;
NET "pb[4]" LOC = P22 | IOSTANDARD = LVTTL;

NET "sevsega[0]" LOC = P57 | IOSTANDARD = LVTTL;
NET "sevsegb[0]" LOC = P58 | IOSTANDARD = LVTTL;
NET "sevsegc[0]" LOC = P66 | IOSTANDARD = LVTTL;
NET "sevsegd[0]" LOC = P67 | IOSTANDARD = LVTTL;
NET "sevsege[0]" LOC = P74 | IOSTANDARD = LVTTL;
NET "sevsegf[0]" LOC = P75 | IOSTANDARD = LVTTL;
NET "sevsegg[0]" LOC = P78 | IOSTANDARD = LVTTL;
NET "sevsegdp[0]" LOC = P80 | IOSTANDARD = LVTTL;

NET "sevsega[1]" LOC = P82 | IOSTANDARD = LVTTL;
NET "sevsegb[1]" LOC = P83 | IOSTANDARD = LVTTL;
NET "sevsegc[1]" LOC = P84 | IOSTANDARD = LVTTL;
NET "sevsegd[1]" LOC = P85 | IOSTANDARD = LVTTL;
NET "sevsege[1]" LOC = P87 | IOSTANDARD = LVTTL;
NET "sevsegf[1]" LOC = P88 | IOSTANDARD = LVTTL;
NET "sevsegg[1]" LOC = P92 | IOSTANDARD = LVTTL;
NET "sevsegdp[1]" LOC = P94 | IOSTANDARD = LVTTL;

NET "sevsega[2]" LOC = P97 | IOSTANDARD = LVTTL;
NET "sevsegb[2]" LOC = P98 | IOSTANDARD = LVTTL;
NET "sevsegc[2]" LOC = P99 | IOSTANDARD = LVTTL;
NET "sevsegd[2]" LOC = P100 | IOSTANDARD = LVTTL;
NET "sevsege[2]" LOC = P101 | IOSTANDARD = LVTTL;
NET "sevsegf[2]" LOC = P102 | IOSTANDARD = LVTTL;
NET "sevsegg[2]" LOC = P104 | IOSTANDARD = LVTTL;
NET "sevsegdp[2]" LOC = P111 | IOSTANDARD = LVTTL;

NET "sevsega[3]" LOC = P114 | IOSTANDARD = LVTTL;
NET "sevsegb[3]" LOC = P115 | IOSTANDARD = LVTTL;
NET "sevsegc[3]" LOC = P116 | IOSTANDARD = LVTTL;
NET "sevsegd[3]" LOC = P117 | IOSTANDARD = LVTTL;
NET "sevsege[3]" LOC = P118 | IOSTANDARD = LVTTL;
NET "sevsegf[3]" LOC = P119 | IOSTANDARD = LVTTL;
NET "sevsegg[3]" LOC = P1120 | IOSTANDARD = LVTTL;
NET "sevsegdp[3]" LOC = P121 | IOSTANDARD = LVTTL;  

Remember if you haven't installed the pulldown resistors to edit the pins in the .ucf with

| PULLDOWN;
or
| PULLUP;

If you want to use the block for anything the connections are as follows. Left being the block pin number and right being the mojo pin number that you should assign in your .ucf:

pin 1 = 29

pin 2 = 51

pin 3 = 32

pin 4 = 41

pin 5 = 34

pin 6 = 35

pin 7 = 40

pin 8 = 33

pin 9 = GND

pin 10 = +V

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    2 Comments

    0
    hydronics
    hydronics

    1 year ago

    Yeah I love the Mojo. I see a lot of comments on the FPGA boards poo poo'ing the programming environment and 'not quite verilog' code they used but it helped me get a very complex project done.