## Introduction: Project 3.1: Majority of 5

How could you find a majority of the vote if each of five voters has a switch to vote for yes or no? The logic is fairly simple and will be used in this project. Any time there are three or more of the five who vote yes, then there is a majority and the LED needs to turn on.

What you need:

- Have completed the previous projects and challenges (all of the previous projects are contained in a collection called EE214).

- Have the Xilinx® Vivado WebPACK™ installed.

- Have your FPGA board set up.

- Be able to define a logic circuit using a truth table.

- Be able to derive a logic equation from a truth table.

- Be able to describe logic functions using Verilog HDL and implement them on an FPGA.

I won't cover all of the basic theory you need but you are interested follow these links:

## Step 1: Background Knowledge

If a truth table is completed for the logic equation, it is a fairly easy step to get a maxterm equation and simplify it with an entered variable K-map. Knowing how to use and read a K-map is a fundamental step in creating a digital circuit with minimum transistors and no redundancies.

If haven't read the module on entered variable k-maps you can find it here.

## Step 2: Define Top Module and I/Os

Start a new project as instructed in previous projects. Use a blank Verilog file and construct a proper XDC file for your board. For this project, we are going to utilize 5 switches for inputs and an LED as an output. The LED will illuminate whenever the majority of voters vote yes.

1 module top(

2 input [4:0] sw,

3 output led

4 );

5

## Step 3: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 1

1. Assume that there are 5 people (A, B, C, D, and E). If three or more of them vote yes, represented by a “1”, the result is 1. Using this information, fill in a K-map to represent the logic expression. It should result in a super K-map as displayed above.

## Step 4: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 2

It is pretty difficult to loop a super K-map, so we need to compress it in order to make looping plausible.

## Step 5: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 3

Now that the K-map has been compressed, it is time to loop it. There is only one variable in this K-map, so we will find loops with the entered variable E first. You can compare your loop result to the graph above. You should have six loops to correspond to the six product terms.

## Step 6: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 4

Now that we have covered the cells with variable E, it is time to see if all of the information in the K-map is looped. By looking at the K-map, we can see that there are a few more loops that we need to create. The column partition of the cell with the value '1' is not covered by a loop in the previous step. In order to create a fully looped K-map these cells need to be looped. When you loop with an entered variable, remember that there contains a smaller K-map with both a 1 and a 0. The sections filled in with a 1 contain a smaller K-map with multiple sections with a 1. In order to complete looping the K-map you must account for all of the sections with a 1. You may check your loops with the graph above. There should be 4 loops corresponding with the 4 product terms.

## Step 7: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 5

From the logic diagram that you have created it is now possible to construct the logic expression in SOP form as follows:

Y = A*B*C+A*B*D+A*C*D+B*C*D+A*B*E+A*D*E+A*C*E+B*C*E+C*D*E+B*D*E

## Step 8: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 6

From this SOP equation you can build a simple assign statement to control the LED wire. The following code uses “&” as the symbol for logic AND and “|” as the symbol for logic OR. This uses “assign” statements, which were discussed in-depth in prior projects. The “assign” statement and the LED will be held at logic high whenever the combinational logic statement is true.

1. assign led = (sw[0] & sw[1] & sw[2]) | // ABC

2. (sw[0] & sw[1] & sw[3]) | // ABD

3. (sw[0] & sw[2] & sw[3]) | // ACD

4. (sw[1] & sw[2] & sw[3]) | // BCD

5. (sw[0] & sw[1] & sw[4]) | // ABE

6. (sw[0] & sw[3] & sw[4]) | // ADE

7. (sw[0] & sw[2] & sw[4]) | // ACE

8. (sw[1] & sw[2] & sw[4]) | // BCE

9. (sw[2] & sw[3] & sw[4]) | // CDE

10. (sw[1] & sw[3] & sw[4]); // BDE

## Step 9: Construct a Minimum Logic Expression From the Truth Table Using K-Map - Step 7

Finally, make sure that the module is closed with “endmodule”.

## Step 10: Verify the Circuit in the Simulator - Step 1

How do we tell if a complex logic circuit is working?

The Verilog code can be simulated using a Verilog test fixture, also called a test bench.

In order to create a test bench you will need to add a simulation source. Right click on Simulation Sources in the project manager sources tab and click edit simulation sets.

## Step 11: Verify the Circuit in the Simulator - Step 2

When the window opens click create file and name the file majority_of_five_test_fixture.

Once the file is created it will be under the Simulation Sources section of the project manager sources tab. Expand this section and double click the file you just created.

The file will contain a template for a module. You can delete everything in this file, we will write the test fixture ourselves.

## Step 12: Verify the Circuit in the Simulator - Step 3

The first line of the test fixture should contain the timescale. You may recognize this line from the other Verilog files we created.

'timescale 1ns / 1ps

The 'timescale compiler directive defines the units used in a delay command, which is simply “#50”. This means that there is a delay for 50 units defined in the 'timescale compiler directive. The value before the backslash is the delay unit and the value after the backslash defines the smallest increment that can be used in the delay.The test fixture block of code is a module just like a typical Verilog module but functioning in test fixture, we artificially manipulate the inputs and can examine how the circuit behaves in simulation.

## Step 13: Verify the Circuit in the Simulator - Step 4

Next we need to declare the test bench. I named the test bench to match the simulation file we created.

The next two lines define the inputs and outputs we are interested in testing. Unlike the circuit that was built as a Verilog Module, a test bench is a module that has no input or output ports. It only has internal signals that are connected to the circuit under test (CUT). It generates inputs for the CUT and senses the outputs of the CUT to verify that the CUT is implemented as specified.

module majority_of_five_test_fixture;

// Inputs

reg [4:0] sw;

// Outputs

wire led;

## Step 14: Verify the Circuit in the Simulator - Step 5

Next we need to instantiate the module that we are testing.The majorityof5 module is instantiated in the test fixture. The input port “sw” of the top module is connected to an internal register called sw as declared in the previous step, the output port led is connected to the wired led. Later projects will go into further detail on instantiating.

majorityof5 uut (

.sw(sw),

.led(led)

);

## Step 15: Verify the Circuit in the Simulator - Step 6

Generating the stimulus in the test bench. In this part of the project, you will start writing code to generate stimulus for the “majority of five” circuit. An initial block is used here to code the stimulus generation. The initial block will be processed only once by the simulator. Before the initial block, we will define an integer k, so that we can loop through all the possible input combinations for the “majority of five” circuit. Inside the initial block, we will initialize all the inputs to zero. A for statement is used to loop through all the input possibilities. One input pattern will be held at the input for 20 ns before updating to the next input pattern. After cycling through all of the possible input patterns, the \$finish command is used to end the simulation. The code is shown as follows:

// Declare loop index variable

integer k;

// Apply input stimulus

initial

begin

sw = 0;

for (k=0; k<32; k=k+1)

#20 sw = k;

#20 \$finish;

end

## Step 16: Verify the Circuit in the Simulator - Step 7

Finish the module with an "endmodule".

The finished module should look like this:

'timescale 1ns / 1ps

module majority_of_five_test_fixture;

// Inputs

reg [4:0] sw;

// Outputs

wire led;

// Instantiate the Unit Under Test (UUT)

majorityof5 uut (

.sw(sw),

.led(led)

);

// Declare loop index variable

integer k;

// Apply input stimulus

initial

begin

sw = 0;

for (k=0; k<32; k=k+1)

#20 sw = k;

#20 \$finish;

end

endmodule

## Step 17: Verify the Circuit in the Simulator - Step 8

In the flow navigator on the left side of the window, under the Simulation heading click Run Simulation and select Run Behavioral Simulation.

## Step 18: Verify the Circuit in the Simulator - Step 9

After the simulation runs the Behavioral Simulation window will appear, but it may not open. Select the tap with an untitled name.

Your Simulation should look like the second image in this step.

In order to see the full simulation shown in the third image, you will need to click zoom fit. Zoom fit is the icon of the magnifying glass with the square around it.

Expand the sw section and you will be able to see the changing values as waveforms.

You can also put down a cursor, the yellow line, and this will show the current values. Notice where I have the cursor in the third image sw 4 through 2 are high so led is high.

Notice that led is held high anytime three or more switches are high. You have now successfully run a Verilog Simulation for Majority of Five!