Introduction: RF Signal Generator 100 KHz-600 MHZ on DDS AD9910 Arduino Shield
How to made low noise, high precision, stable RF generator ( with AM, FM Modulation) on Arduino.
Supplies
1. Arduino Mega 2560
2. OLED Displays 0.96"
3. DDS AD9910 Arduino Shield https://gra-afch.com/catalog/arduino/dds-ad9910-a...
Step 1: Hardware Installation
Putting it together
1. Arduino Mega 2560
2. OLED Displays 0.96"
3. DDS AD9910 Arduino Shield
https://gra-afch.com/catalog/arduino/dds-ad9910-arduino-shield/
Step 2: Installing Software
We take the firmware from here and compile in the arduino IDE
Step 3: Adjustment
A 40 MHz generator was used on our board, so we make such settings
Step 4: We Get the Result Much Better Than on Board From China!
We get the result much better than on board from China!
There were a lot of harmonics and spurious on the screen at board from chine, and their level reached -25 dBm! And this is despite the fact that according to the documentation by Analog Devices to AD9910 the level of harmonics should not exceed -60 dBm. But on this board harmonics around -60 dBm! This is a good result!
Phase Noise
This parameter is very important and interesting for those who buy DDS. Since the intrinsic phase noise of DDS is obviously less than that of PLL generators, the final value is highly dependent on the clock source. In order to achieve the values stated in the datasheet on AD9910, when designing our DDS AD9910 Arduino Shield, we strictly adhered to all recommendations from Analog Devices: PCB layout in 4 layers, separate power supply of all 4 power lines (3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog). Therefore, when buying our DDS AD9910 Arduino Shield, You can focus on the data from the datasheet on the AD9910.
Figure 16 shows the noise level when using the built-in PLL in DDS. The PLL multiplies the frequency of a 50 MHz generator by 20 times. We use a similar frequency - 40 MHz (x25 Multiplier) or 50 MHz (x20 Multiplier) from TCXO which gives even more stability.
And figure 15 shows the noise level when using an external reference clock 1 GHZ, with the PLL off.
Comparing these two plots, for example, for Fout = 201.1 MHz and the internal PLL turned on at 10 kHz carrier offset, the phase noise level is -130 dBc @ 10 kHz. And with the PLL off and using external clocking, the phase noise is 145 dBc @ 10kHz. That is, when using an external clock phase noise by 15 dBc better (lower).
For the same frequency Fout = 201.1 MHz, and the internal PLL turned on at 1 MHz carrier offset, the phase noise level is -124 dBc @ 1 MHz. And with the PLL off and using external clocking, the phase noise is 158 dBc @ 1 MHz. That is, when using an external clock phase noise by 34 dBc better (lower).
Conclusion: when using external clocking, You can get much lower phase noise than using the built-in PLL. But do not forget that in order to achieve such results, increased requirements are put forward to the external generator.
Step 5: Plots
Plots with Phase Noise
