VHDL One Minute Stopwatch

This is a tutorial on how to build a one minute stopwatch using VHDL and a Basys 3 board. Such a device is ideal for games where each player has a maximum of one minute to make their move. The stopwatch accurately displays seconds and milliseconds on the seven segment display, starting at 0 seconds and 0 milliseconds, up to 60 seconds and 0 milliseconds. Two buttons are also used: the central button, used to start, stop, and continue the timer, and the right button, used to restart the timer. When the device is compared side-by-side with the built-in stopwatch of a smart phone, the accuracy of the clock is noticeable.

Step 1: Obtain Hardware/Software

1. Basys 3 Artix-7 FPGA Trainer Board from Digilent with Micro-USB to USB Cable

2. Vivado 2016.2 Design Suite from Xilinx

Step 2: Block Diagram

This circuit is constructed behaviorally and uses built-in Xilinx components, but can also be described structurally, as shown by the general structural diagram above. From the diagram, it can be seen that the circuit is driven by two frequency dividers. One of the frequency dividers runs at 1 centisecond and drives the cathode counter that are used as the numbers displayed on the seven-segment display. The second frequency divider runs at 240Hz and is used to drive the anode counter that rotates through the anodes so that all the numbers display correctly on the seven-segment display. The encoder takes the cathode logic from the cathode counter and the anode logic from the anode counter, and encodes it to the output's cathode and anode that run the seven-segment display. The function of this encoder is for the cathode output to change every time the anode output changes. The cathode output cannot be run independently from the counter because the anodes must rotate through the 4 separate digits.

Step 3: Project Module

Firstly, a process block for CEN is made so that when a Button Press is detected, the ENABLE will toggle. This serves as the stop/start of the cathode counter.

In the next process block, the centisecond and 240Hz clock signals are set so that their respective counters increase by 1 every time the internal 100mHz clock reaches a rising edge. Once the centisecond counter reaches 500000, it would reset back to 0. Meanwhile the 240Hz counter would reset once the count reaches 41667.

For the cathode section of the code, if ENABLE is '0' the cathode counting will pause. If the reset button is pressed during this time, then all the counts reset to "0000". Meanwhile, if ENABLE is '1', the cathode counting will continue until the cathode count reaches 60.00, in which it triggers the stop signal to be '1'. The stop signal routes back to the CEN process block and causes ENABLE to be '0' while the stop signal is '1' and will not change until the reset button is pressed.

Finally, the seven segment display is set up by having the 4 anodes correctly connected with each of their 8 cathodes to display their respective digits 0-9 simultaneously.

Step 4: Constraints

This constraints file connects the specified inputs and outputs from VHDL into the necessary, physical parts of the Basys board. For this project, the components includes the four anodes and each of their eight cathodes for the seven segment display, the internal 100 mHz clock, the center button, and the right button.

Step 5: Test

Once you have completed the code, you can now program the FPGA via the USB cable. The seven segment display should show 0.00. Test to see if the buttons work by pressing the central button to start the timer until it reaches 60.00 and stops; anytime in between, you can press the central button again to pause it. Once it is paused, you can press the right button to reset the timer back to 0.00. If everything is working correctly, congratulations you have just built a one minute timer!